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When we introduced our DDR SDRAM, it was revolutionary and pioneering technology. DDR allows applications to transfer data on both the rising and falling edges of a clock signal, doubling bandwidth and vastly improving performance over SDR SDRAM. To achieve this functionality, we use a 2n-prefetch architecture where the internal data bus is double the size of the external data bus, so data capture can happen two times each clock cycle.

By Density

Density Width Voltage Clock Rate Package Op. Temp.
1Gb x16 2.5V 167 MHz TSOP -40C to +85C
512Mb x8, x16, x4 2.5V, 2.6V 167 MHz, 200 MHz FBGA, TSOP -40C to +85C, 0C to +70C, -40C to +105C
256Mb x8, x16 2.5V, 2.6V 167 MHz, 200 MHz TSOP, FBGA -40C to +85C, 0C to +70C
View Full DDR Part Catalog

By Application


Power Calculator
DDR SDRAM System-Power Calculator
  • File Type: ZIP
  • Updated: 01/14/2010
Technical Notes
Describes the initialization sequence and configurable device parameters.
  • File Type: PDF
  • Updated: 08/27/2010


Compatibility Guide

Micron compatibility guide for NXP® Platforms

  • File Type: PDF
  • Updated: 08/16/2017
Compatibility Guide

Micron® DRAM & Flash Memory Support for Ambarella® Platforms

  • File Type: PDF
  • Updated: 03/22/2017
Compatibility Guide

This overview shows Micron DRAM and Flash Memory valdiation and support for Xilinx Platforms.

Compatibility Guide

Micron® Flash & DRAM Memory Support for Intel® FPGA Platforms

  • File Type: PDF
  • Updated: 02/06/2017