Micron DDR5 delivers up to 2x the memory bandwidth1 compared to DDR4, which is required to feed the accelerating growth of CPU cores in the modern data center.

The Advantages of DDR5

Micron DDR5: Offering More Than 2X the Effective Bandwidth

DDR5 will offer up to 2x the effective bandwidth when compared to its predecessor DDR4, helping relieve this bandwidth per core crunch.

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Micron DDR5: Next-Generation Memory Transforming Data Into Insight

Watch how Micron DDR5 addresses the memory bandwidth per CPU challenge and transforms available data into insight.

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More Performance

Micron DDR5 memory delivers up to 5x performance2 compared to DDR4 for Deep Learning, which is required to feed the continued growth of CPU cores in the data center for AI, HPC and Enterprise workloads.


Improved Reliability

Micron DDR5 is designed to improve reliability across the data center with features like on die error correction code to correct single bit errors automatically and makes the host CPU / GPU more efficient.


Scalable Configurations

Micron DDR5 memory is validated for 16/32/64 GB and 24/48/96 GB with major CPU vendors. As a result, Enterprise and Cloud Service Providers can enable flexible configurations optimized for TCO.

Deep Learning: Dual socket 3rd Gen Intel Xeon CPU 8380 (40 cores) with Micron 64 GB DDR4 3200 MHz system with 1 TB total capacity; dual socket 4th Gen Intel Xeon CPU 8490H (60 cores) with 1 Advanced Matrix Extension activated with Micron DDR5 64 GB DIMMS 4800 MHz system with 1 TB total capacity; this result is based on testing done at Micron Austin Labs. ML Perf BERT (bert-large-uncased Language Model) dataset yielded of 4.8x with the DDR5 system using the dataset inference_results_v2.1/closed/Intel/code/bert-99/pytorch-cpu at master · mlcommons/inference_results_v2.1 · GitHub

Micron DDR5 Technology Enablement Program

The DDR5 Technical Enablement Program (TEP) is a program that offers a path into Micron to gain early access to technical information and support, electrical and thermal models as well as DDR5 products to aid in the design, development and bring-up of next-generation computing platforms.

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Select Density
  • 16Gb
Range: 16Gb
  • Width
    x8, x16
  • Voltage
  • Package
  • Clock Rate
    2400 MHz
  • Op. Temp.
    0C to +95C

Part Catalog for Micron DDR5

Micron DDR5 is game-changing memory for the data center, available in a variety of densities at 4800 MT/s.

View the Micron DDR5 Part Catalog

Featured Resources

Micron DDR5 Delivers Next-Gen Performance and Reliability for the 4th Gen Intel®️ Xeon®️ Scalable Processor Family

Micron DDR5 improves workloads across the data center today while enabling future infrastructure growth.

Micron DDR5 Memory Now Available for 4th Gen AMD EPYC Processors

The combination scales up to 2x the performance for select HPC memory-bound workloads.

Podcast: Micron DDR5 for the Data Center

Listen to a podcast discussing the impact of Micron DDR5 memory and the promise it holds for data center and cloud workloads.

Boost HPC Workloads With Micron DDR5 and 4th Gen AMD EPYC Processors 

Micron DDR5 with 4th Gen AMD EPYC processors runs HPC workloads two times faster than systems using DDR4 and AMD “Zen 3” architecture, all while allowing double the memory bandwidth per core over these previous-generation systems.

Ecosystem Partners

Collaborating with strategic partners is what we do. Our relationships with preferred partners and key enablers are our top priority. Through those relationships, we're building ecosystems that promote connections and co-development efforts that lead to better solutions for our customers.

Advantages of Migrating to DDR5

DDR5 is the next evolution in DRAM, bringing a robust list of new features geared to increase reliability, availability, and serviceability (RAS); reduce power; and dramatically improve performance. Some of the key feature differences between DDR4 and DDR5 are as follows:

Feature/Option DDR4 DDR5 DDR5 Advantage
 Data rates  1600-3200 MT/s  4800-8800 MT/s  Increases performance and bandwidth
 VDD/VDDQ/VPP   1.2/1.2/2.5   1.1/1.1/1.8   Lowers power
 Internal VREF  VREFDQ  VREFDQ, VREFCA, VREFCS   Improves voltage margins, reduces BOM costs
 Device densities    2Gb-16Gb    16Gb-64Gb    Enables larger monolithic devices 
 Prefetch    8n   16n    Keeps the internal core clock low
 DQ receiver equalization   CTLE  DFE  Improves opening of the received DQ data
 eyes inside the DRAM
 Duty cycle adjustment (DCA)   None   DQS and DQ  Improves signaling on the transmitted DQ/DQS pins
 Internal DQS delay
 None   DQS interval oscillator   Increases robustness against environmental changes 
 On-die ECC  None  128b+8b SEC, error check and scrub   Strengthens on-chip RAS
 CRC   Write   Read/Write    Strengthens system RAS by protecting read data 
 Bank groups (BG)/banks   4 BG x 4 banks (x4/x8)
 2 BG x 4 banks (x16)
 8 BG x 4 banks (16-64Gb x4/x8)
 4 BG x 4 banks (16-64Gb x16) 
 Improves bandwidth/performance
 Command/address interface   ODT, CKE, ACT, RAS,
 CAS, WE, A<X:0>

 Dramatically reduces the CA pin count

 ODT  DQ, DQS, DM/DBI   DQ, DQS, DM, CA bus    Improves signal integrity, reduces  BOM costs 
 Burst length  BL8 (and BC4)   BL16 
 (and BC8 OTF) 
 Allows 64B cache line fetch with only 1 DIMM subchannel. 
 MIR (“mirror” pin)   None  Yes  Improves DIMM signaling
 Bus inversion   Data bus inversion (DBI)  Command/address inversion (CAI)   Reduces VDDQ noise
 CA training, CS training   None   CA training, CS training   Improves timing margin on CA and CS pins  
 Write leveling training modes   Yes  Improved  Compensates for unmatched DQ-DQS path
 Read training patterns   Possible with the MPR  Dedicated MRs for serial
 (userdefined), clock and LFSR
 -generated training patterns
 Makes read timing margin more robust
 Mode registers  7 x 17 bits  Up to 256 x 8 bits
 (LPDDR type read/write) 
 Provides room to expand
 PRECHARGE commands   All bank and per bank  All bank, per bank, and same bank   PREsb enables precharging a bank in each BG
 REFRESH commands   All bank   All bank and same bank  REFsb enables refreshing a bank in each BG
 Loopback mode  None   Yes  Enables testing of the DQ and DQS signaling