The world’s leading processor and server vendors have been delivering new platforms that enhance performance generation after generation. But the ability for processor improvements alone to meet performance and reliability needs has been waning because DDR4 memory cannot supply enough bandwidth as processor core counts continue to grow. This is where the industry introduction of DDR5 memory is a critical enhancement — breaking down the memory wall and allowing servers with a hundred or more cores to access scalable, high-performance memory and unlock full performance and efficiency. But not all data center customers could use this breakthrough DDR5 technology as it required platform support.
Not anymore! On Jan. 10, 2023, Intel® launched the 4th Gen Intel® Xeon® Scalable processor family platforms, which include their first server processors that support DDR5 memory (among a raft of new features from Intel). These platforms are intended to provide higher data throughput for mission critical, in-memory storage and networking workloads. There is a plethora of server vendors eagerly awaiting the ability to provide these new high-performance systems to the data center customers who rely on Intel platforms. So, it’s big news!
DDR5 for all
Micron is eager to help address the performance challenges faced by our customers, enabling them with our leading Micron DDR5 memory for improved performance and efficiency of their data center workloads. Our collaboration with Intel prioritizes enabling best-in-class user experiences from client to data center and ensures we are able to validate memory with Intel Xeon Scalable processors at scale and available at launch. Intel, Micron and leading server manufacturers have validated DDR5 RDIMMs with capacities of 16GB, 32GB and 64GB with the latest 4th Gen Intel Xeon Scalable processor family — offering unprecedented performance and scale with these new systems.
Although DRAM memory is highly standardized (thanks to the hard work of Micron and others who are developing robust standards and specifications via JEDEC) it still takes a great deal of collaboration across the ecosystem to build a high-performance, reliable server solution. Technology has never been more critical as data center solutions have become disaggregated, but it does not happen overnight. The journey to DDR5 memory and 4th Gen Intel Xeon platform solutions has been some time in the making.
The essential role of enablement
Micron has long recognized the critical role of early component and platform enablement to allow for smooth time to market for systems vendors. That’s why Micron’s innovative Technical Enablement Program (TEP) for DDR5 was created in 2020. In this program, we provide early access to technical specs, thermals and other critical information to support our partners as they design, develop and bring up DDR5-based computing platforms for the data center, client, intelligent edge and cloud. To date, more than 160 unique companies in the ecosystem have registered for the program to build, test and validate their components and systems.
Today’s announcement with Intel showcases how we worked with them— from power on of the processor, initial validation and shared engineering samples to production release so that Micron memory is part of their volume validation tests. As a result, 108 configurations of Micron memory are validated with 4th Gen Intel Xeon Scalable processors. This work was essential to allow a streamlined customer experience and choice of solution scale to meet customer needs.
While we’re all pleased to see the first DDR5 platforms reach the market, we are just getting started! The collaboration with Intel and the ecosystem continues as we test and validate next generations of DDR5 (JEDEC has defined specifications for future speed bumps to 5600, 6400 and 8800 MT/s).
Naturally, with a new-generation platform, we expect improved performance. And the 4th Gen Intel Xeon Scalable processor platform with Micron DDR5 memory delivers! Micron and our ecosystem partners will be publishing additional papers and blogs showcasing the performance gains enabled by DDR5 with latest-generation processors, but to give you a sense of what’s in store, consider this example:
SPECjbb runs 1.48X faster with Micron DDR5.
The SPECjbb®2015 benchmark has been developed from the ground up to measure performance based on the latest Java application features. It’s relevant to all audiences who are interested in Java server performance, including Java virtual machine (JVM) vendors, hardware developers, Java application developers, researchers and members of the academic community. This workload is representative of an e-commerce workload.
The DDR4 system is capable of 205 GB/s memory bandwidth, and the DDR5 system is capable of 307 GB/s.
Software stack used for testing this workload:
- SUSE Enterprise Linux (SLES) 15 SP4 for the DDR4 and DDR5 system
- SPECjbb 2015 version 1.03
- Dell R750 system equipped with Micron DDR4 3200 MHz 64 GB RDIMMS and dual-socket 3rd Gen Intel Xeon Scalable processors with 40 cores and 3.4 GHz
- Dell R760 system equipped with Micron DDR5 4800 MHz 64GB RDIMMS and dual-socket 4th Gen Intel Xeon Scalable processor with 56 cores and 3.8 GHz
- DDR4 system is a Dell PowerEdge R750 dual socket with 3rd Gen Intel Xeon Scalable 8380 processors with Micron DDR4 3200 MHz which is capable of 408 GB/sec provided a result of 135269 Critical Java Operations Per Second.
- DDR5 system is a Dell PowerEdge R760 dual socket with 4th Gen Intel Xeon Scalable 8480 processors with Micron DDR5 4800 MHz which is capable of 614 GB/sec provided a result of 200288 Critical Java Operations Per Second.
While everyone wants and expects added performance, data is so valuable that customers appreciate enhancements that benefit the reliability, integrity and availability of their data and services. Micron DDR5 brings additional value here, as it includes several new capabilities that augment traditional server RAS capabilities:
- On-die error correction code (ODECC)
- Error check and scrub (ECS)
- Same bank refresh
Here’s a simple overview of how on-die ECC works: For every 128 bits of data in a DDR5 write operation, an 8-bit code is generated and stored by the DRAM. When the read operation occurs, the DRAM evaluates the combined data string and corrects any single bit errors.
As an additional benefit, DDR5 also introduces an error check and scrub (ECS) feature where the device will internally correct data when a single bit error is detected. ECS can be run manually or automatically within the recommended 24-hour period. When the error scrub is complete, DDR5 can report the number of errors that were corrected.
Lastly, low-latency applications can use new same bank refresh capabilities to enhance application availability and responsiveness. Where DDR4 locks and refreshes all banks at the same time, DDR5 provides greater access through granular bank refresh capabilities. Same bank refresh enables refreshing a single bank at a time, keeping all the other banks groups available so that the processor can access the data.
These are just a few examples of new capabilities available on DDR5, but there’s more goodness that comes with this new memory. You can learn more about it here.
DDR5 is ubiquitous
With Intel’s latest announcement of 4th Gen Intel Xeon Scalable processors, the availability of DDR5-enabled platforms has grown enormously. Customers of all the leading data center platforms now have access to new systems offering incredible levels of performance, efficiency and reliability. Micron will continue to work with the full ecosystem of partners to ensure these platforms and solutions have the right Micron DDR5 memory options to deliver real customer value by ensuring that data continues to flow unimpeded as processor core counts grow.