Memory

Micron Launches Technology Enablement Program to Advance DDR5 Adoption

By Brian Drake - 2020-07-14

What an exciting time — advancements continue for bringing DDR5 to market as the next generation of DRAM memory to address the increasing complexity of data center workloads!

As a refresher, CPU core counts are increasing. So, enabling continued compute performance gains in the data center requires the performance advantages of DDR5 to maintain available bandwidth per CPU core. DDR5, along with the additional compute, will be instrumental in extracting value and insight from the explosion of data being generated in the world today.

 

So, what recent events have us so thrilled?

JEDEC has officially released DDR5 SDRAM standards

To start, thanks to all the hard work from JEDEC and its many members involved, including Micron, in driving revision 1.0 to closure!

The specification release highlights new features, functionalities, AC and DC characteristics, packages, ball/signal assignments and density support in DDR5. Some of these details have been discussed in multiple forums in the past, but with its public release, details are now available for more in-depth discussion with non-JEDEC members. This availability of information further opens the door for DDR5 education, collaboration and enablement in the market.

 

Micron announces the Technology Enablement Program (TEP) to advance DDR5 adoption

Alongside that news from JEDEC, Micron launched an exciting new Technology Enablement Program (TEP).

What is TEP?

TEP is a program for approved partners that offers a path into Micron to gain early access to technical information and support. Data sheets will be readily available, as well as behavioral/functional models, signal integrity models and thermal models, to aid in product development. In addition to the easy access to commonly used models, partners can find training materials, technical support, technical marketing briefs and blogs — all located on a single website!

But why stop there? Being enrolled also gives the partner access to DDR5 component and module samples, including early opportunity to check out products as they become available.

TEP reaches beyond Micron products and resources. The program also provides access to other ecosystem partners who can aid in chip- and system-level design. For more on the ecosystem partners enabling DDR5, check out the ecosystem portal.

Who is eligible? How do I apply?

To find the answers to these questions, go to www.micron.com/ddr5. The short answer on eligibility is that the program is targeted at CPU and ASIC designers, system architects and designers, OEMs, integrators, distribution and early enterprise or data center customers who are:

  1. Bringing a DDR5-based product to market
  2. Evaluating a DDR5-enabled platform

DDR5 is ready to help answer the big questions

As someone who has been involved in discussions with both customers and enablers for the last couple of years, I welcome these announcements. These events will further accelerate the DDR5 enablement process, and I look forward to the future engagements that TEP specifically will make possible.

DDR5 is here, and as I have mentioned in previous blogs, it is exciting to ponder how this increased memory bandwidth, along with increased compute power, will help answer today’s biggest questions in science and medicine, research and development, and other expanding technology areas.

Micron is ready to engage with those interested in TEP and to help enable this next-generation DRAM memory, DDR5. Visit www.micron.com/ddr5 to learn more.

Brian Bradford

Brian Drake

Brian leverages 14 years of DRAM expertise to lead strategy development in the Data Center segment with a focus on enabling DDR5 solutions for hyperscale customers. Before moving to his current role within Micron Brian spent 6 years in Product Engineering where his time was split between leading and/or contributing to teams responsible for developing, enabling, and maintaining DRAM products. Four years prior to joining Micron, he held roles within Infineon and Qimonda as a DRAM test program engineer.
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