Since the advent of the smart phone, people have become accustomed to and conditioned to expect graphical user interfaces, instant-on responsiveness, portability, constant connectivity, and more from their modern day electronic devices. The expectation is becoming the norm as we cram more and more smart electronics into our cars, our living space, and our lives. Meeting the needs of the demanding digital user calls for high performance system buses for firmware code execution, data storage, working data processing, sensor data, etc. Current system bus interfaces often require the tradeoff between performance and footprint, either the high performance of a high pin-count parallel interface or the small active signal footprint of a serial interface.
The Xccela Consortium is an industry association championed by Micron to promote the Xccela Bus as an open-standard digital interconnect and data communications bus suitable for volatile and nonvolatile memories as well as other types of integrated circuits (e.g. MCUs, SoCs, ADCs, etc.). The charter of the consortium is to define the Xccela Bus interface specifications and common command protocols for those devices that will reside and communicate on the Xccela Bus. The consortium is open to all companies, whether they are semiconductor manufacturers, systems and electronics companies (customers), test equipment companies, etc.
In its first iteration, the Xccela Bus is a high-speed, high-performance Octal SPI bus that uses eight data lines for command and data transfer. The bus is synchronous and supports both single-transfer rate (STR) operation, where one byte of data is transferred every clock cycle, and dual-data rate (DDR) operation in which two bytes of data are transferred every clock cycle. The DDR operation requires the use of a data strobe signal (DQS). The Xccela Bus supports clock frequencies up to 200MHz and data transfer rates up to 400MB/sec (3.2Gbps).
Initially, interested companies can send their requests to Xccela Consortium.