DDR5 delivers next-generation performance in the data center with 4th Gen AMD EPYC™ processors

Brian Drake | November 2022

DDR5 delivers next-generation performance in the data center with 4th gen AMD EPYC™ processors

Today is an exciting day in the evolution of the data center with the introduction of the EPYC™ 9004 Series Processor-based platforms. Micron is thrilled to see the continued advancement in the deployment of data center platforms using next-generation memory. With the introduction of the 4th Gen AMD EPYC Processors comes the availability of up to 96 CPU cores and 12 memory channels per socket, a 50% increase in both metrics from the previous AMD generation. An additional critical enhancement included in the AMD next-gen platform is the transition to DDR5 memory, which enables the full platform performance and efficiency required by today’s data-centric workloads. With 12 available memory channels, this enables a maximum theoretical bandwidth of 460GB/s at the introduction data rate of 4800MT/s.

“4th Gen AMD EPYC Processors continue to raise the bar for workload performance in the modern data center while simultaneously delivering exceptional energy efficiency. 4th Gen AMD EPYC Processors will transform our customers’ data center operations by accelerating time to value, driving lower total cost of ownership, and helping enterprises to address their sustainability goals,” said Ram Peddibhotla, corporate vice president, EPYC product management, AMD.

Driving insight from data

It’s no secret that businesses need to drive insight from the growing volume of data captured every second of the day. AI-enabled applications such as health care, smart manufacturing, research and development, and autonomous driving all rely on massive amounts of data. Extracting insights from huge volumes of data from disparate sources requires complex algorithms running on high-performance servers featuring balanced compute, storage and scalable memory bandwidth.

For over a decade, servers have continued to pack more processing cores into CPUs without any change in memory architectures, but at the cost of unbalanced performance. The result has been that memory bandwidth per CPU core has been decreasing, making memory a bottleneck to current data center architectures. Server architectures must address this imbalance to allow processors to readily access huge volumes of data in memory to operate more efficiently.

Enter DDR5

With the launch of the 4th Gen AMD EPYC processor platform, the underlying server architecture addresses this imbalance and is where Micron DDR5 becomes a game-changing technology. Architected for the data center with higher data rates, twice the bank groups, twice the banks, double the burst length and improved refresh schemes, this allows DDR5 to deliver higher effective bandwidth and bus efficiency vs. DDR4. In addition to these improvements, DDR5 also enables two independent channels per module, effectively doubling the available memory channels in the system. These enhancements will drive compute performance and efficiency growth, by enabling capability of approximately two times the memory performance increase relative to DDR4 at introduction, to tackle data-intensive workloads such as AI training, in-memory databases and complex visualization.

DDR5 is not only about significantly improving available bandwidth but is also critical to the continued ability to scale reliably to meet the growing density requirements in data center or enterprise servers. DDR5 optimizes core DRAM timing to enable higher density monolithic devices (up to 64Gb) and adds on-die error correction with an error check and scrub feature to further improve data integrity and remove some of that burden from the system itself.

Much more detail on these DDR5 features can be read about in these technical briefs posted on Micron® DDR5 SDRAM: New Features, Micron® DDR5: Key Module Features.

Enabling the ecosystem

With CPU, memory, I/O technologies all progressing in parallel, it is critical that the ecosystem collaborates to assure readiness of all system components. Micron has been doing its part to enable other market leaders to be ready with DDR5. Through Micron’s Technology Enablement Program (TEP), we are providing access to critical design specifications, models, documentation and samples to CPU and ASIC designers, systems architects and designers, OEMs, integrators, distributors and early enterprise and data center customers. These resources go beyond Micron products and resources and provide access to other ecosystem partners who can aid in chip and system-level design. For more information, check out our ecosystem portal.

Driving insight with next-generation memory

With data increasingly viewed as a critical asset, collection, storage and interpretation is a growing imperative for enterprises. Industries around the globe are leveraging data for insight and innovation. DDR5 makes processing that data faster and more efficient. The timing for the introduction of DDR5 in the data center could not be better, as current forecasts show that the amount of data created globally will more than double by 2025 to reach a staggering 180 zettabytes.1 We are proud to support AMD in the release of their new 4th generation platforms to lead the momentum for DDR5 adoption in the data center.

To meet the growing demands of data center workloads, Micron continues to drive the data center ecosystem to enable the DDR5 transition and beyond. We’re innovating to meet the evolving memory demands of our datacentric world: Where workloads grow in data intensity and algorithms continue to evolve in complexity. As we navigate this new world, Micron remains a committed and valued partner, delivering DDR5 for the data center today and working with partners to address the challenges of tomorrow.

Visit to learn more.

1Source: IDC, Global DataSphere, March 2021

Senior Manager, Business Development, Cloud

Brian Drake

Brian leverages 17 years of DRAM expertise to lead strategy development in the Data Center segment with a focus on enabling DDR5 solutions for hyperscale customers. Before moving to his current role within Micron Brian spent 6 years in Product Engineering where his time was split between leading and/or contributing to teams responsible for developing, enabling, and maintaining DRAM products. Four years prior to joining Micron, he held roles within Infineon and Qimonda as a DRAM test program engineer.