Memory

The Road to Autonomous Driving

By Robert Bielby - 2.12.19

While we are still quite some time away from self-driving cars being ubiquitous, several announcements at this year’s Consumer Electronics Show (CES) indicate an acceleration in the deployment of ADAS features and associated technologies that are essential in realizing level 5 autonomous driving. Specifically, there was buzz around a new category of ADAS announced by several vendors: level 2+. Level 2+ is slated to provide many of the key lifesaving features that are essential components of level 5 autonomous driving, but at price points that are suitable for mass deployment. Level 2+ is intended to address situations that include driving in stop-and-go traffic on congested highways—taking actions that humans might be unable to perform to avoid accidents.

And while level 2+ was a buzz at CES, this does not mean that there has been any ease on the focus to deliver the promise of fully autonomous level 5 capabilities. Many of the major auto OEMs continue to have their sights set on, and continue to message their intent to demonstrate, level 5 autonomous vehicles at the upcoming 2020 Olympics. The semiconductor industry has responded to the technology demands associated with supporting level 5 capabilities through the continued introduction of products with the extreme compute performance required to address this space.

In a recently released white paper, Achronix Semiconductor highlights the capabilities of their newest line of Speedcore eFPGAs in addressing the needs of self-driving vehicles. Their white paper, entitled “How to Meet Power, Performance and Cost for Autonomous Vehicle Systems using Speedcore eFPGAs,” highlights both the challenges of addressing the self-driving space and the unique benefits of their embedded FPGA and standalone FPGA products in addressing those challenges. Central to this white paper and their associated product capabilities is “the need for speed” to address the extensive computational requirements of autonomous driving.

While breakthroughs in the application of AI have been key to realizing the long-term vision of self-driving cars, the performance required to support the underlying Dynamic Neural Network (DNN) translates into computing levels well in excess of 50 teraflops—a task Achronix’s next generation FPGA family can readily address. Keeping that compute pipeline constantly filled is essential to realizing this level of system performance, and is one of the many justifications for adopting the industry’s highest performance memory technology—GDDR6. The introduction of automotive compliant GDDR-6 is proving to be a disruptive technology which provides the essential memory bandwidth to ensure AI compute pipelines are not stalled and deliver the requisite AI compute performance to realize the higher levels of autonomous driving up to L5. Through the use of GDDR6, Achronix’s next generation FPGA devices are able to support a total of 4 terabytes per second (tb/s) of memory bandwidth in a practical footprint that can be readily deployed in the most demanding automotive applications and environments.

With over 42 percent market share and 28 years of commitment to the automotive market, Micron has taken industry leadership in the announcement of the delivery of automotive-qualified GDDR6—an essential ingredient to realizing the vision of self-driving cars. It’s clear that Micron’s leadership in memory technology, including GDDR6, in conjunction with leading SoC suppliers such as Achronix will have a profound effect on shaping the future of the automotive market.

For more information on Micron’s GDDR6, go to https://www.micron.com/products/graphics-memory.

More information regarding the Achronix white paper can be found here: https://www.achronix.com/doc/how-to-meet-power-performance-and-cost-for-autonomous-vehicle-systems-using-speedcore-efpgas-wp015/?t=27&d=1

Rob Peglar

Robert Bielby

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