Should the DLL be disabled?
Although in some cases the DRAM may work with the DLL off, this mode of operation is not documented nor supported by JEDEC. Therefore, each DRAM design may behave differently when configured to run with the DLL disabled. Micron does not support or guarantee operation with the DLL disabled. Running the DRAM with the DLL disabled may cause the device to malfunction and/or violate some DRAM output timing specifications.
Should DDR2 SDRAM always have ODT turned on?
It’s not recommended, as the SDRAM reads will lose voltage margin; but technically, it is allowed.
Is VREF allowed to float during self refresh mode?
No, it must be maintained at VDDQ/2.
What is the DDR2 RDQS pin for?
The sole purpose of RDQS is to support the use of a x8-based RDIMM in a x4-based RDIMM system. The RDQS pin enables a x8 DDR2 SDRAM to emulate two x4s.
Will the device run at a slow clock (well under the slowest data sheet speed)?
For a READ operation, the DRAM edge-aligns the strobe(s) with the data. Most controllers sense the strobe to determine where the data window is positioned. This fine strobe/data alignment requires that each DRAM have an internal DLL. The DLL is tuned to operate for a finite frequency range, which is identified in each DRAM data sheet. Running the DRAM outside these specified limits may cause the DLL to become unpredictable.
The DRAM is tested to operate within the data sheet limits. Micron does not suggest or guarantee DRAM operation outside these predefined limits.
What is the maximum clock rate for DDR2 when it’s used with a single-ended DQS?
The answer depends mostly on design implementation. As long as the data setup and holds have 150ps or more of margin and there’s a fast slew rate, a single-ended DQS should be OK.
What is the difference between 1.5V DDR2 SDRAM and 1.55V DDR2 SDRAM?
1.5V DDR2 SDRAM is not backward compatible to 1.8V operating systems, and the 1.55V DDR2 SDRAM is.
Is the ridge down the middle of the underside of FBGA packages conductive?
No, only designated balls are conductive.
Are there any timing specification differences between 1.5V DDR2 SDRAM and 1.8V DDR2 SDRAM?
Are there any timing specification differences between 1.55V DDR2 SDRAM and 1.8V DDR2 SDRAM?
Yes, DLL-controlled output specs require some derating.
Are there any supply voltage savings with 1.5V DDR2 SDRAM versus 1.55V DDR2 SDRAM?
Yes, the 1.5V DDR2 SDRAM uses about 15–20 percent less current than the 1.55V DDR2 SDRAM.
Can DDR2-1066 be used with two slots?
Using DDR2-1066 with two slots is unrealistic; simulations have not shown acceptable margins.
Is DDR2-1066 a JEDEC standard?
Not yet, but it’s in process.
How much power does the Vref power pin draw?
The Vref pin does not draw any power, only leakage current, which is less than 5µA.
Can you explain how on-die termination (ODT) affects power consumption?
On-die termination (ODT) power is very application-dependent. ODT is also variable, depending on the setting in the EMR of the DRAM. Use the DDR2 power calculator to determine the values.
In a point-to-point system, ODT would only be active on WRITE cycles, and would not consume power during idle and READ cycles. On-board termination would consume power in these instances. ODT power should be about 2–3 percent of the total DDR2 DRAM power in a typical application.