On DDR, what happens when DQS write postamble (tWPST) maximum specification is exceeded? What problems could this cause?
The tWPST maximum specification is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly.
On DDR, can the allowed jitter tolerance be larger than +/-150ps if we use a clock of 120 MHz instead of 133 MHz? Can the allowed jitter tolerance be larger if the device is faster?
The part may have more tolerance or margin to jitter than 150ps at 133 MHz, but Micron still has the same specification for all speeds. Micron does not relax jitter specifications for a lower speed.
Is VREF required during self refresh? I would like to put DDR memory in self refresh mode and turn off power to the CPU (the system is battery-operated). Can I disable VREF and still have correct self refresh operation?
Yes. VREF is required during self refresh. All DDR components' on-chip address counters are still operational during self refresh mode, so VDD must be maintained within the stated data sheet limits.
Again, VREF must not be disabled after the DDR memory is put into self refresh mode. Doing so could easily result in inadvertently exiting self refresh.
You should understand that VREF draws almost no power; any current drawn by VREF is negligible when compared to VTT and the core VDD. DDR components typically use a differential pair common source amplifier as their SSTL_2 input receiver. Because the VREF pin is used primarily as an input to this circuit, its current draw is low. It is so low, in fact, that the device’s input leakage current (~5µA) can be considered the maximum current requirement for the VREF pin. Typical VTT power is drawn from other places on the board and depends on the other components used on the module/system in addition to DRAM devices.
On DRAM, can a READ or WRITE command be given instead of a refresh?
If all of the different row addresses are read or written within the refresh time (tREF), a refresh need not be performed. (The different row addresses are the same number of rows as the number of REFRESH cycles. For example, in the case of 8,192/64ms, the number of rows equal 8,192.) With DRAM, selecting row addresses causes the same action as a refresh, so a REFRESH command need not be executed.
What is the maximum junction temperature at which DDR SDRAM functionality is guaranteed?
Please refer to page 3 of Micron’s technical note on thermal applications: TN-00-08
. If functionality or operation is not a concern, refer to storage temperature specification limits on the part’s data sheet.
What is the difference between no connect (NC), no function (NF), and do not use (DNU) pins? How should external connections to them be handled?
An NC (no connect) pin indicates a device pin to which no internal connection is present or allowed. Micron recommends that no external connection be made to this pin. However, if a connection is inadvertently made, it will not affect device operation. Sometimes NC pins could be reserved for future use. Refer to the part’s data sheet to confirm whether the pin is reserved for future use.
An NF (no function) pin indicates a device pin that is electrically connected to the device but for which the signal has no function in the device operation. Micron strongly recommends that no external connection be made to this pin.
A DNU (do not use) pin indicates a device pin to which there may or may not be an internal connection but to which no external connections are allowed. Micron requires that no external connection be made to this pin. Refer to the part’s data sheet for more details.
On DRAM, can unused DQ (data) pins be left floating?
Micron recommends that unused data pins be tied HIGH or LOW. Because Micron uses CMOS technology in DRAM manufacturing, letting them float could leave the pins susceptible to noise and create a random internal input level. Unused pins can be connected to VDD or ground through resistors.
Can you provide a brief description of the necessary circuit functionality we would need to employ to transition from EDO to SDRAM technology?
Synchronous DRAM, as its name suggests, is a synchronous device and is a little different from EDO. SDRAM are directly tied to the same system clock that drives all of the other subsystems.
SDRAM uses a dual-bank architecture—an interleave technique that essentially allows one cell to be read while another is being prepared for a cell access. This "cell hopping" eliminates downtime between cell activities and provides good performance improvement. Since the SDRAM will operate at higher speeds, attention needs to be paid to signal layout, including transmission line techniques such as series-terminating resistors. A consequence of signal layout could be noise due to faster clocks, crosstalk, etc.
At the very least, an SDRAM controller is necessary for transitioning from EDO to SDRAM technology.
Can I get samples?
Yes. Talk to your service representative.
A customer uses a DDR -6T part at 333 MHz. Can he substitute a faster speed grade part (DDR400, -5B) without encountering problems due to the 2.6V operation? Can the customer run the part at -75 speeds?
Yes, all speed grades are backward-compatible. So, -5B can run at -6T timing and -6T voltage levels (2.5V). At DDR400 speeds, Micron parts require (in compliance with JEDEC standard) Vdd = VddQ = 2.6V ±0.1V. At slower speed grades (DDR333 through DDR200), the Micron parts are backward compatible, only requiring Vdd = VddQ = 2.5V ±0.2V.
Do I need a separate voltage regulator to supply Vref power?
How Vref is supplied depends on the system design. Many multi-drop systems (where there are several modules and a need for Vtt on the system board) already have a designated voltage regulator for DDR memory. In this case, the voltage regulator may have a dedicated tap for Vref. Other systems that incorporate point-to-point memory typically use a simple voltage divider resistor network between Vdd and Vss.
How long does Micron plan to support DDR?
Micron has an extensive customer base across all four densities (256Mb–1Gb) of DDR and plans to support it for several years. Contact your local Micron sales representative for direction on the preferred part number to qualify.
How long does Micron plan to support 3.3V SDRAM?
Micron has an extensive customer base across all four densities (64–512Mb) of SDR and plans to support it for several years. Contact your local Micron sales representative for direction on the preferred part number to qualify.
Does Micron provide VHDL models for DDR parts?
No. Micron no longer supports VHDL models. We can, however, provide a generic 8 Meg x 8 model (MT46LC8M8) that can be scaled to the desired model dimensions. It’s a good starting point for building a compatible DDR model. To obtain this file, contact your Micron representative or a Micron applications engineer.
You could also contact Denali or Synopsys to obtain one of their models. Or you could use a suitable multi-language simulator (like Modelsim) that cosimulates Verilog and VHDL and then download our Verilog model.