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DDR: Still an Ideal Choice for Many New Designs

When we introduced our DDR SDRAM, it was revolutionary and pioneering technology. DDR allows applications to transfer data on both the rising and falling edges of a clock signal, doubling bandwidth and vastly improving performance over SDR SDRAM. To achieve this functionality, we use a 2n-prefetch architecture where the internal data bus is double the size of the external data bus, so data capture can happen two times each clock cycle.

Because DDR continues to be the ideal choice for many new designs, we're committed to long-term product support and availability.

  • Broad offering of densities and configuration to suit your design needs
  • Industry-standard packages make it easy to design in
  • Long-term product support: We’re committed to leveraging our proven technology, premier quality, and industry-leading manufacturing efficiencies to provide DDR for many years to come.
  • Technical support: We strive to provide the best technical support in the memory business
  • Extended operating ranges for optimum functionality in extreme environments
  • A complete portfolio of RoHS 6/6-compliant DDR parts, plus a set of 5/6-compliant products

.

Featured Article

DDR to DDR2

DDR to DDR2

Compared to DDR, DDR2 offers extraordinary performance, reduces power consumption, maximizes DRAM throughput, improves signal integrity, and optimizes flexibility...

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DDR Toolbox

DDR Toolbox

Micron's Designer's Toolbox provides resources for designers developing system-level products that take advantage of the DDR SDRAM memory architecture. From presentations and design resources to industry standards and specifications--you'll find the information you need in the Toolbox.

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For DDR SDRAM (16)
Title & Description Secure ID# Updated Type
Industrial and Multimarket Application Memory Flyer: (PDF 398.61 KB) Our extensive and stable portfolio of IMM-focused memory solutions empower technology developments in automotive, industrial, medical, manufacturing, and other multimarket segments. 09/2014 Product Flyer
Termination for Point-to-Point Systems: (PDF 356.29 KB)Provides a basic understanding of transmission line theory that is important to insure signal integrity in today's high-speed digital systems. TN-46-06 03/2011 Technical Note
Initialization Sequence for DDR SDRAM: (PDF 294.95 KB)Describes the initialization sequence and configurable device parameters. TN-46-08 08/2010 Technical Note
DDR SDRAM System-Power Calculator: (ZIP 55.81 KB) 01/2010 Power Calculator
DDR System Design Considerations: (PDF 3.46 MB)DDR overview 12/2009 Presentation
Competitive DDR Memory Subsystems: (PDF 2.64 MB)DDR milestones and platform design 12/2009 Presentation
Designing for 1Gb DDR SDRAM: (PDF 175.43 KB)Provides system designers with essential information relevant to utilizing the 1Gb double data rate (DDR) synchronous dynamic random access memory (SDRAM). TN-46-09 11/2009 Technical Note
Thinning Considerations for Wafer Products: (PDF 73.58 KB)Information on optimal wafer-thinning processes to meet specific customer requirements TN-00-19 10/2009 Technical Note
Mobile LPDRAM Unterminated Point-to-Point System Design: Layout and Routing Tips: (PDF 552.55 KB)Provides guidance for the development of multilayer board designs TN-46-19 11/2008 Technical Note
Hardware Tips for Point-to-Point System Design: (PDF 376.6 KB)Provides hardware tips for point-to-point system design, termination, and layout TN-46-14 06/2008 Technical Note
Mobile LPDDR Versus Standard DDR SDRAM: (PDF 432.44 KB)An overview of the functional and mechanical differences between low-power and standard DDR and a description of exclusive features of LPDDR TN-46-15 12/2007 Technical Note
DDR SDRAM Point-to-Point Simulation Process: (PDF 330.05 KB)Covers rarely addressed areas of the DDR SDRAM point-to-point simulation process TN-46-11 07/2005 Technical Note
Calculating DDR Memory System Power: (PDF 336.91 KB)Describes how to calculate DDR memory system power. TN-46-03 03/2005 Technical Note
Decoupling Capacitor Calculation for a DDR Memory Channel: (PDF 151.37 KB)Provides a decoupling capacitor calculation for a DDR memory channel TN-46-02 12/2004 Technical Note
DDR333 Design Guide for Two-DIMM Unbuffered Systems: (PDF 5.93 MB)Describes DDR333 design guide for two-DIMM unbuffered systems TN-46-07 12/2002 Technical Note
General DDR SDRAM Functionality: (PDF 254.8 KB)Describes DDR SDRAM functionality TN-46-05 12/2001 Technical Note
For DRAM (15)
Title & Description Secure ID# Updated Type
HMC Part Numbering System: (PDF 59 KB)Part numbering guide for Hybrid Memory Cube 10/2014 Part Numbering Guide
DRAM Component Part Numbering System: (PDF 46.77 KB)Part numbering guide for DDR4/DDR3/DDR2/DDR/SDR SDRAM, Mobile LPDRAM, and RLDRAM components 10/2014 Part Numbering Guide
Legacy LPDRAM Part Numbering System: (PDF 114.47 KB)Part numbering guide for legacy LPDDR2 and LPDRR3 PoP and FBGA components 05/2014 Part Numbering Guide
SEMI Wafer Map Format: (PDF 114.26 KB)Micron has adopted the wafer map file format approved by Semiconductor Equipment and Materials International (SEMI). With SEMI formatting, Micron's customers can be confident they will always receive consistent, compatible, reliable map files. TN-00-21 03/2014 Technical Note
Routing Guidelines for Micron’s HMC-15G-SR: (PDF 3.3 MB)Provides sound methods, proven solutions, and detailed PCB layout guidelines to enable successful designs using Micron’s HMC. TN-43-03 HMC TN-43-03 06/2013 Technical Note
Recommended Soldering Parameters: (PDF 173.37 KB)Defines the recommended soldering techniques and parameters for Micron Technology, Inc., products. TN-00-15 12/2012 Technical Note
Bypass Capacitor Selection for High-Speed Designs: (PDF 481.9 KB)Describes bypass capacitor selection for high-speed designs. TN-00-06 03/2011 Technical Note
Micron Wire-Bonding Techniques: (PDF 66.13 KB)This technical note provides guidance on wire bonding techniques for both nickel-palladium (NiPd) and aluminum (Al) bond pads on Micron products. TN-00-22 11/2010 Technical Note
Uprating of Semiconductors for High-Temperature Applications: (PDF 428.33 KB)Describes the issues associated with temperature uprating and the risks involved in using components and/or systems outside the manufacturer's environmental specifications TN-00-18 05/2010 Technical Note
Accelerate Design Cycles with Simulation Models: (PDF 206.91 KB)Micron supplies the tools and guidelines necessary to verify new designs prior to layout. This technical note discusses software model support, signal integrity optimization, and logic circuit design. TN-00-09 02/2010 Technical Note
Understanding Signal Integrity: (PDF 1.64 MB)Describes how memory design, test, and verification tools can be used to the greatest advantage, from conception of a new product through end of life TN-00-20 12/2009 Technical Note
IBIS Behavioral Models: (PDF 163.98 KB)Micron has been a member of the IBIS Open Forum for many years and fully supports the IBIS specification. IBIS models for most Micron products are available for download from the Micron Web site. TN-00-07 11/2009 Technical Note
Understanding Quality and Reliability Requirements for Bare Die Applications: (PDF 142.04 KB)Describes the quality and reliability requirements for bare die applications TN-00-14 10/2009 Technical Note
FBGA Date Codes: (PDF 22.36 KB)Date codes for FBGA-packaged components 08/2005 Part Numbering Guide
FBGA Decoder: Micron's FBGA Part Marking Decoder makes it easier to understand part marking. Tool
For Products and Support (14)
Title & Description Secure ID# Updated Type
Micron Component and Module Packaging: (PDF 1.35 MB)Explanation of Micron packaging labels and procedures. CSN-16 11/2014 Customer Service Note
Product Marks/Product and Packaging Labels: (PDF 1.58 MB)Explains product part marking, and product and packaging labels. CSN-11 10/2014 Customer Service Note
Shipping Quantities: (PDF 1.22 MB)Provides standard part quantities for shipping. CSN-04 03/2014 Customer Service Note
RMA Procedures for Packaged Product and Bare Die Devices: (PDF 76.22 KB)Outlines standard returned material authorization (RMA) procedures, as well as the differences associated with bare die RMAs. CSN-07 01/2014 Customer Service Note
Wafer Packaging and Packaging Materials: (PDF 591.42 KB)Provides complete shipping and recycling information about each of the materials used for shipping Micron's products. CSN-20 11/2013 Customer Service Note
Thermal Applications: (PDF 246.79 KB)Describes some considerations in thermal applications for Micron memory devices TN-00-08 07/2013 Technical Note
Moisture Absorption in Plastic Packages: (PDF 97.08 KB)Describes shipping procedures for preventing memory devices from absorbing moisture and recommendations for baking devices exposed to excessive moisture TN-00-01 02/2013 Technical Note
Micron BGA Manufacturer's User Guide: (PDF 388.76 KB)Provides information to enable customers to easily integrate both leading-edge and legacy Micron's ball grid array (BGA) packages into their manufacturing processes. It is intended as a set of high-level guidelines and a reference manual describing typical package-related and manufacturing process-flow practices. CSN-33 12/2012 Customer Service Note
Electronic Data Interchange: (PDF 52.45 KB)Describes EDI transmission sets, protocol, and contacts. CSN-06 11/2012 Customer Service Note
PCN/EOL Systems: (PDF 79.21 KB)Explains Micron's product change notification and end-of-life systems. CSN-12 04/2012 Customer Service Note
Lead Frame Package User Guidelines: (PDF 245.66 KB)Discusses Micron's lead-frame package options CSN-30 05/2011 Customer Service Note
ESD Precautions for Die/Wafer Handling and Assembly: (PDF 120.81 KB)Describes the benefits of controlling ESD in the workplace, including higher yields and improved quality and reliability, resulting in reduced manufacturing costs. CSN-24 08/2010 Customer Service Note
Micron KGD Definitions: (PDF 65.52 KB)Describes the testing specifications and parameters for Micron's KGD-C1 and KGD-C2 DRAM die. CSN-22 07/2009 Customer Service Note
Bare Die SiPs and MCMs: (PDF 151.06 KB)Describes design considerations for bare die SiPs and MCMs. CSN-18 04/2009 Customer Service Note

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DDR SDRAM FAQs (14)

On DDR, what happens when DQS write postamble (tWPST) maximum specification is exceeded? What problems could this cause?
The tWPST maximum specification is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly.
On DDR, can the allowed jitter tolerance be larger than +/-150ps if we use a clock of 120 MHz instead of 133 MHz? Can the allowed jitter tolerance be larger if the device is faster?
The part may have more tolerance or margin to jitter than 150ps at 133 MHz, but Micron still has the same specification for all speeds. Micron does not relax jitter specifications for a lower speed.
Is VREF required during self refresh? I would like to put DDR memory in self refresh mode and turn off power to the CPU (the system is battery-operated). Can I disable VREF and still have correct self refresh operation?
Yes. VREF is required during self refresh. All DDR components' on-chip address counters are still operational during self refresh mode, so VDD must be maintained within the stated data sheet limits. Again, VREF must not be disabled after the DDR memory is put into self refresh mode. Doing so could easily result in inadvertently exiting self refresh. You should understand that VREF draws almost no power; any current drawn by VREF is negligible when compared to VTT and the core VDD. DDR components typically use a differential pair common source amplifier as their SSTL_2 input receiver. Because the VREF pin is used primarily as an input to this circuit, its current draw is low. It is so low, in fact, that the device’s input leakage current (~5µA) can be considered the maximum current requirement for the VREF pin. Typical VTT power is drawn from other places on the board and depends on the other components used on the module/system in addition to DRAM devices.
On DRAM, can a READ or WRITE command be given instead of a refresh?
If all of the different row addresses are read or written within the refresh time (tREF), a refresh need not be performed. (The different row addresses are the same number of rows as the number of REFRESH cycles. For example, in the case of 8,192/64ms, the number of rows equal 8,192.) With DRAM, selecting row addresses causes the same action as a refresh, so a REFRESH command need not be executed.
What is the maximum junction temperature at which DDR SDRAM functionality is guaranteed?
Please refer to page 3 of Micron’s technical note on thermal applications: TN-00-08. If functionality or operation is not a concern, refer to storage temperature specification limits on the part’s data sheet.
What is the difference between no connect (NC), no function (NF), and do not use (DNU) pins? How should external connections to them be handled?
An NC (no connect) pin indicates a device pin to which no internal connection is present or allowed. Micron recommends that no external connection be made to this pin. However, if a connection is inadvertently made, it will not affect device operation. Sometimes NC pins could be reserved for future use. Refer to the part’s data sheet to confirm whether the pin is reserved for future use. An NF (no function) pin indicates a device pin that is electrically connected to the device but for which the signal has no function in the device operation. Micron strongly recommends that no external connection be made to this pin. A DNU (do not use) pin indicates a device pin to which there may or may not be an internal connection but to which no external connections are allowed. Micron requires that no external connection be made to this pin. Refer to the part’s data sheet for more details.
On DRAM, can unused DQ (data) pins be left floating?
Micron recommends that unused data pins be tied HIGH or LOW. Because Micron uses CMOS technology in DRAM manufacturing, letting them float could leave the pins susceptible to noise and create a random internal input level. Unused pins can be connected to VDD or ground through resistors.
Can you provide a brief description of the necessary circuit functionality we would need to employ to transition from EDO to SDRAM technology?
Synchronous DRAM, as its name suggests, is a synchronous device and is a little different from EDO. SDRAM are directly tied to the same system clock that drives all of the other subsystems. SDRAM uses a dual-bank architecture—an interleave technique that essentially allows one cell to be read while another is being prepared for a cell access. This "cell hopping" eliminates downtime between cell activities and provides good performance improvement. Since the SDRAM will operate at higher speeds, attention needs to be paid to signal layout, including transmission line techniques such as series-terminating resistors. A consequence of signal layout could be noise due to faster clocks, crosstalk, etc. At the very least, an SDRAM controller is necessary for transitioning from EDO to SDRAM technology.
Can I get samples?
Yes. Talk to your service representative.
A customer uses a DDR -6T part at 333 MHz. Can he substitute a faster speed grade part (DDR400, -5B) without encountering problems due to the 2.6V operation? Can the customer run the part at -75 speeds?
Yes, all speed grades are backward-compatible. So, -5B can run at -6T timing and -6T voltage levels (2.5V). At DDR400 speeds, Micron parts require (in compliance with JEDEC standard) Vdd = VddQ = 2.6V ±0.1V. At slower speed grades (DDR333 through DDR200), the Micron parts are backward compatible, only requiring Vdd = VddQ = 2.5V ±0.2V.
Do I need a separate voltage regulator to supply Vref power?
How Vref is supplied depends on the system design. Many multi-drop systems (where there are several modules and a need for Vtt on the system board) already have a designated voltage regulator for DDR memory. In this case, the voltage regulator may have a dedicated tap for Vref. Other systems that incorporate point-to-point memory typically use a simple voltage divider resistor network between Vdd and Vss.
How long does Micron plan to support DDR?
Micron has an extensive customer base across all four densities (256Mb–1Gb) of DDR and plans to support it for several years. Contact your local Micron sales representative for direction on the preferred part number to qualify.
How long does Micron plan to support 3.3V SDRAM?
Micron has an extensive customer base across all four densities (64–512Mb) of SDR and plans to support it for several years. Contact your local Micron sales representative for direction on the preferred part number to qualify.
Does Micron provide VHDL models for DDR parts?
No. Micron no longer supports VHDL models. We can, however, provide a generic 8 Meg x 8 model (MT46LC8M8) that can be scaled to the desired model dimensions. It’s a good starting point for building a compatible DDR model. To obtain this file, contact your Micron representative or a Micron applications engineer. You could also contact Denali or Synopsys to obtain one of their models. Or you could use a suitable multi-language simulator (like Modelsim) that cosimulates Verilog and VHDL and then download our Verilog model.

DRAM FAQs (8)

What is a "bank"?
A bank is an array of memory bits. Multiple arrays or banks are contained within a DRAM component. Depending on density, DRAM components may consist of 4 or 8 banks. For example, a bank may consist of 32 million rows, 4 bits across. This would equate to 128 megabits. Four of these banks in a single DRAM component would yield a 512Mb component.
What is the impedance tolerance of the driver in match-impedance mode relative to the expected value base on the perfect reference resistor connected to ZQ pin?
The impedance tolerance of the driver is ±15 percent.
Does thermal information change for IT parts?
Thermal information includes temperature limits and thermal impedance values. Temperature limits do change for IT parts (TC, TJ, and TA), but thermal impedance values (θJA, θJB, and θJC) do not because thermal impedance depends primarily on the package.
My design was based on a specification stating the JTAG was relative to VDD (1.8V), but now we’ve discovered that JTAG is actually relative to VDDQ (1.5V). It’s a fairly significant board spin to change this; what do I risk by leaving the design as-is? I assume that the specification is still for VDDQ + 0.3V = 1.8V, but with CMOS parts there’s no way I can guarantee that it won’t swing past that on transitions.
Your particular board design should not be a cause of major concern. The pins can handle the VDD voltage regardless of the VDDQ voltage.
Should the ECC memory chip share chip select and CKE signals with the other two main memory chips in our point-to-point application?
The ECC chip(s) should share the same CKE and CS# as the other devices because they are accessed as the same piece of data.
Is there a recommended lowest working frequency for SDRAM?
Because SDRAM does not have a DLL, there is no recommended lowest frequency. SDRAM parts will work at very low frequencies if all data sheet specifications are met. It is important to maintain a good slew rate, however, since a very slow slew rate will affect setup and hold-time transitions. Also, for operating frequencies of 45 MHz, tCKS = 3.0ns. For more information, see TN-48-09.
Can the SDRAM clock frequency be changed?
Micron SDRAM data sheets require that the clock frequency be constant during access or precharge states (READ, WRITE, tWR, and PRECHARGE commands). At other times frequency should not matter much because there is no DLL in SDRAM however, we do not recommend it. Lowering SDRAM frequency is OK even if you are not doing an LMR and CAS latency change. In case of increasing frequency, ensure tCK and CAS latency specifications are met. In either case, all other data sheet timing specifications should be adhered to.
Can CKE be tied HIGH throughout SDRAM operation (initialization and normal operation)?
JEDEC does not specify the exact state of CKE during initialization; it is supplier specific. Micron strongly recommends CKE be kept at an LVTTL logic LOW before applying a stable CLK signal. During normal operation, CKE can be tied HIGH. The initial LOW state of CKE prevents parts from receiving an illegal LMR command, which could put the part into an unknown or unexpected state.

Products and Support FAQs (1)

Who do I contact if I have questions about my buymicron.com order?
If you have any questions about your order, contact buymicron.com.

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