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MLC NAND Standard Page Save
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The Best Solution for Mainstream Storage Applications

Multilevel cell (MLC) is the most popular NAND Flash, providing the right combination of price and performance for a wide range of high-density applications.

Storing 2 bits per cell, MLC NAND is a popular solution for applications that need higher-density storage, such as SSDs, tablets, smart phones, and other wireless devices. MLC devices offer twice the capacity of SLC NAND in the same die area and are a good choice for cost efficiency. 

We also offer an Enterprise MLC product that provides increased endurance for write-centric applications.

Enterprise MLC

Extending MLC Cycling Capabilities

Enterprise MLC (eMLC) NAND is designed for write-intensive enterprise applications that need a more cost-effective solution than SLC NAND. It’s an ideal storage solution for transaction-intensive data servers and enterprise appliances.

Our eMLC products enable endurance levels well beyond standard MLC products and work with either advanced ECC or BCH controllers. In BCH systems, our 20nm eMLC products are qualified for up to 10,000 WRITE/ERASE cycles with 40b/1KB BCH. While LDPC implementations and system requirements vary, 25,000 cycles may be achievable.

Let us help you get the most out of your enterprise storage application. We’ll leverage the latest processor, controller, and interface designs to provide you with the best possible solution.

3-bit-per-cell MLC NAND Flash

High Speed and Improved Endurance

Micron’s 20nm and 16nm NAND products with MLC+ modes are designed to provide the performance of high-speed MLC while boosting endurance—making MLC+ an ideal solution for performance-oriented SSDs.

MLC+ NAND provides higher endurance than standard MLC but without the usage limitations of eMLC. When paired with advanced ECC methods, MLC+ can exceed the standard 3,000 WRITE/ERASE cycles. Well-engineered systems using advanced ECC methods can see endurance levels over 10,000 PROGRAM/ERASE cycles. SSDs that implement MLC+ capabilities can reach endurance specifications of 3 to 5 fills per day.

These parts also support ONFI’s high-speed synchronous interface (which improves data transfer rates) and come in standard BGA packages of 1 to 16 die stacks. Contact Micron for more information about adopting MLC+ in your design.

  • Density leadership:  Our 20nm 128Gb MLC is the highest-density die on market today, providing up to 1Tb in a single package.
  • Solid performance:  The best balance of endurance, ECC complexity, and performance.
  • Cost-effective:   As the leading technology node, 20nm NAND provides 2-bit-per-cell efficiency.
  • NAND Flash expertise:  Our leadership in process technology and design, as well as our stringent testing, ensures optimum performance and reliability.
  • Technical support:  Our multistage technical assistance helps you design in some of the industry’s highest-quality memory with ease. We work with chipset vendors, OS designers, and other enablers to ensure that our parts are optimized for your design.

Featured Article

Improving SSD Performance

Storage Switzerland

Learn how better flash management can maximize the performance and longevity of your SSD.

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20nm NAND Delivers Big for Enterprise Market

Skyera CEO, Radoslav Danilak, Ph.D., discusses how Micron’s 20nm NAND Flash memory delivered next-generation performance and capacity, enabling his company’s new Skyhawk enterprise solid state storage system to achieve price parity with conventional disk space storage systems.



For MLC NAND (2)
Title & Description Secure ID# Updated Type
Networking Solutions Guide: (PDF 240.27 KB)This guide outlines Micron’s various solutions—from DRAM components and modules to NOR and NAND Flash to solid state drives (SSDs)—available for networking applications. 06/2013 Product Flyer
Enterprise NAND Flash Memory Flyer: (PDF 149.19 KB)Discusses features and advantages of Micron Enterprise NAND Flash memory. 08/2010 Product Flyer
For NAND Flash (93)
Title & Description Secure ID# Updated Type
Industrial and Multimarket Application Memory Flyer: (PDF 398.61 KB) Our extensive and stable portfolio of IMM-focused memory solutions empower technology developments in automotive, industrial, medical, manufacturing, and other multimarket segments. 09/2014 Product Flyer
NAND Flash Controller on Spartan-3: (PDF 567.97 KB)This technical note describes the Micron NAND Flash controller, techniques for interfacing the NAND Flash device with a processor and use of the Micron glueless interface to interface a processor with NAND Flash memory. TN-29-06 07/2014 Technical Note
Technical Note: Using Chip Enable Pin Reduction in NAND Flash Memory Devices: (PDF 201.34 KB)This technical note describes how to enable and use the chip enable pin reduction feature in Micron's NAND Flash memory devices and discusses reduction limitations based on NAND package and system configuration. TN-29-77 05/2014 Technical Note
SEMI Wafer Map Format: (PDF 114.26 KB)Micron has adopted the wafer map file format approved by Semiconductor Equipment and Materials International (SEMI). With SEMI formatting, Micron's customers can be confident they will always receive consistent, compatible, reliable map files. TN-00-21 03/2014 Technical Note
Legacy NAND Flash Part Numbering System: (PDF 27.39 KB)Part numbering guide for Micron Legacy NAND Flash products. 03/2014 Part Numbering Guide
NAND Flash Part Numbering System: (PDF 35.52 KB)Part numbering guide for Micron NAND Flash products. 03/2014 Part Numbering Guide
Technical note: Using the Block Lock Feature on MT29F NAND Flash Memory Devices: (PDF 162.3 KB)This technical note describes the block lock feature on Micron's MT29F NAND Flash memory devices. TN-2976 02/2014 Technical Note
Nonvolatile Memory for Multiple Markets : (PDF 177.33 KB)Describes why Micron NVM is the best fit for your applications 01/2014 Product Flyer
Flash + Controller Part Numbering System for Embedded Applications: (PDF 27.16 KB)Part numbering guide for Embedded eMMC products. 11/2013 Part Numbering Guide
Compatibility Guide for Micron Software Device Drivers Available on micron.com: (PDF 90.31 KB)This document lists the compatible NOR and NAND devices for the software device drivers available for download from micron.com. 11/2013 Product Flyer
NOR | NAND Flash Guide: Selecting a Flash Storage Solution : (PDF 210.68 KB)This guide describes the various Flash technologies offered by Micron to help system designers select the optimal Flash solution for their needs. 10/2013 Product Flyer
Enabling On-Die ECC NAND with JFFS2: (PDF 219.39 KB)This technical note addresses altering the the MTD/NAND layer for the on-die ECC NAND device. TN-29-75 08/2013 Technical Note
Routing Guidelines for Micron’s HMC-15G-SR: (PDF 3.3 MB)Provides sound methods, proven solutions, and detailed PCB layout guidelines to enable successful designs using Micron’s HMC. TN-43-03 HMC TN-43-03 06/2013 Technical Note
Software Device Drivers for MT29F Micron NAND Flash Memory: (PDF 339.4 KB)This technical note explains how to use Micron’s MT29F NAND Flash memory software device drivers, which are the low-level drivers (LLDs) that manage the hardware functionality of the NAND Flash memory devices. Download the low-level driver described in this document here. TN-29-72 05/2013 Technical Note
Recommended Soldering Parameters: (PDF 173.37 KB)Defines the recommended soldering techniques and parameters for Micron Technology, Inc., products. TN-00-15 12/2012 Technical Note
Next Generation Flash + Controller Part Numbering System: (PDF 24.1 KB) 11/2012 Part Numbering Guide
ONFI Member Flyer: (PDF 1.01 MB) 08/2012 Product Flyer
Flash + Controller Part Numbering System: (PDF 28.46 KB) 08/2012 Part Numbering Guide
High-Performance NAND Flyer: (PDF 272.79 KB)Fast, Reliable, Robust – Diverse Performance Options for Demanding Applications 07/2012 Product Flyer
Enabling Software BCH Error Correction Code (ECC) on a Linux Platform: (PDF 688.7 KB)This technical note addresses applications using existing 1-bit ECC processors to enable Micron MT29F1GxxABxDA, MT29F2GxxABxEA, MT29F4GxxABxDA, and MT29F1GXXABXEA NAND Flash memory devices with software BCH ECC. TN-29-71 04/2012 Technical Note
Optimize your system designs using Flash memory: (PDF 6.18 MB) 04/2012 Presentation
ONFI 2.3a Gold: (PDF 2.7 MB) 10/2011 Other Documents
Software Device Drivers for Large Page Micron NAND Flash Memory Devices: (PDF 624.45 KB)This technical note explains how to use the Micron large page NAND Flash memory software device drivers. Download the low-level driver described in this document here. TN-29-62 10/2011 Technical Note
NAND 201: An Update on the Continued Evolution of NAND Flash: (PDF 641.28 KB)Chronicles the developments in NAND technology from 2006 through early 2011. 09/2011 White Paper
Physical NAND Flash Security: (PDF 2.32 MB) 08/2011 Presentation
Looking Ahead at Flash Memory: (PDF 6.43 MB) 08/2011 Presentation
400 MT/s NAND Interface Solutions: (PDF 2 MB)Why are 400 MT/s speeds necessary? Presentation from Flash Memory Summit 2011. 08/2011 Presentation
System Benefits of EZ-NAND/Enhanced ClearNAND Flash: (PDF 1.77 MB) 08/2011 Presentation
NAND Flash Comparisons for Mobile: (PDF 4.84 MB) 08/2011 Presentation
FMS2011 Keynote: (PDF 2.41 MB) 08/2011 Presentation
Current and Emerging Memory Technology Landscape: (PDF 2.78 MB) 08/2011 Presentation
Enabling a Flash Memory Device into the Linux MTD: (PDF 528.81 KB)The technical note introduces the Linux memory technology device (MTD) architecture and provides a basis for understanding how to enable new devices and new features into the Linux MTD. TN-00-25 05/2011 Technical Note
TN-29-51: Migrating from 50-Series to 60-Series SLC NAND Flash Devices: (PDF 121.59 KB)Migrating from 50-Series to 60-Series SLC NAND Flash Devices; M58A, M59A, M50A, M68A, M69A, M60A TN-29-51 05/2011 Technical Note
TN-29-57: Migrating from 50-Series to 60-Series SPI NAND Flash Devices: (PDF 164.87 KB)Supplements the product change notification (PCN) covering the transition from Micron 50-series (50nm) to 60-series (34nm) single-level cell (SLC) SPI NAND Flash devices. TN-29-57 05/2011 Technical Note
Bypass Capacitor Selection for High-Speed Designs: (PDF 481.9 KB)Describes bypass capacitor selection for high-speed designs. TN-00-06 03/2011 Technical Note
ONFI 3.0 Spec: (PDF 4.3 MB) 03/2011 Other Documents
TN-29-58: ONFI NV-DDR2 Design Guide: (PDF 685.04 KB)Rev. A TN-29-58 03/2011 Technical Note
TN-29-56: Enabling On-Die ECC for OMAP3 on Linux/Android OS: (PDF 331.14 KB)Enabling NAND On-Die ECC for OMAP3 Using Linux/Android OS with YAFFS2. M60A, M69A, M68A. TN-29-56 12/2010 Technical Note
Micron Wire-Bonding Techniques: (PDF 66.13 KB)This technical note provides guidance on wire bonding techniques for both nickel-palladium (NiPd) and aluminum (Al) bond pads on Micron products. TN-00-22 11/2010 Technical Note
Wear Leveling in NAND Flash Memory: (PDF 213.59 KB)This technical note describes the recommended wear leveling algorithm to be implemented in the FTL software for NAND Flash memory. TN-29-61 10/2010 Technical Note
Software Device Drivers for Very Large Page Micron NAND Flash Memory: (PDF 405.64 KB)This technical note explains how to use the Micron very large page NAND Flash memory software device drivers. Download the low-level driver described in this document here. TN-29-65 10/2010 Technical Note
Software Device Drivers for Small Page Micron NAND Flash Memory: (PDF 889.73 KB)This technical note explains how to use the Micron small page NAND Flash memory software drivers. Download the low-level driver described in this document here. TN-29-64 10/2010 Technical Note
Migrating from a Chip Enable Care to a Don't Care NAND Flash Memory: (PDF 265.78 KB)The purpose of this application note is to highlight the differences between Chip Enable don’t care and Chip Enable care devices. AN2365 10/2010 Technical Note
Garbage Collection in SLC NAND Flash Memory: (PDF 207.37 KB)This technical note describes the recommended garbage collection algorithm to be implemented in the Flash Translation Layer (FTL) software for single-level cell (SLC) NAND Flash memory devices. AN1821 10/2010 Technical Note
Error Correction Code in SLC NAND Flash: (PDF 486.67 KB)This technical note describes how to implement error correction code (ECC) in Micron small page and large page single-level cell (SLC) NAND Flash memory that can detect 2-bit errors and correct 1-bit errors per 256 or 512 bytes. TN-29-63 10/2010 Technical Note
Bad Block Management in NAND Flash Memory: (PDF 317.81 KB)This technical note explains how to recognize factory-generated bad blocks and manage bad blocks that develop during the lifetime of NAND Flash memory. TN-29-59 10/2010 Technical Note
TN-29-52: Migrating 1Gb 48nm and 2Gb/4Gb 57nm SLC NAND Flash Memory to 34nm: (PDF 180.46 KB)Provides guidelines for migrating 1Gb 48nm and 2Gb/4Gb 57nm SLC, large-page NAND Flash memory to 34nm technology (M60A, M69A & M68A) TN-29-52 10/2010 Technical Note
TN-29-17: NAND Flash Design and Use Considerations: (PDF 226.04 KB)Describes design and use considerations for NAND Flash memory, focusing on bad-block identification and error correction. TN-29-17 09/2010 Technical Note
NAND Choices Flyer: (PDF 141.94 KB)A quick look at choosing the right NAND solution for your design needs 08/2010 Product Flyer
Uprating of Semiconductors for High-Temperature Applications: (PDF 428.33 KB)Describes the issues associated with temperature uprating and the risks involved in using components and/or systems outside the manufacturer's environmental specifications TN-00-18 05/2010 Technical Note
NAND Flash 101 - An Introduction to NAND Flash and How to Design It In to Your Next Product: (PDF 968.5 KB)Provides an introduction to NAND Flash and how to design it into your next product. Rev. B TN-29-19 04/2010 Technical Note
NAND Flash Performance Improvement Using Internal Data Move: (PDF 219.17 KB)NAND data management capabilities and higher system performance through NAND Flash internal data moves TN-29-15 03/2010 Technical Note
On-Die ECC NAND Flash Flyer: (PDF 173.52 KB)With four times or more th density of NOR, On-Die EC NAND is a great alternative to NOR for many embedded designs. 03/2010 Product Flyer
NAND Flash Performance Increase with PROGRAM PAGE CACHE MODE Command: (PDF 266.14 KB)This technical note discusses the benefits of PROGRAM PAGE CACHE MODE operations over normal PROGRAM PAGE operations. It also provides specific timing examples and instructions for performing PROGRAM PAGE CACHE MODE operations. Rev. C TN-29-14 02/2010 Technical Note
Accelerate Design Cycles with Simulation Models: (PDF 206.91 KB)Micron supplies the tools and guidelines necessary to verify new designs prior to layout. This technical note discusses software model support, signal integrity optimization, and logic circuit design. TN-00-09 02/2010 Technical Note
Determining NAND Flash Ready/Busy Status: (PDF 136.48 KB)Systems that utilize NAND Flash memory can use either the ready/busy pin or the status register to determine whether a Micron® NAND Flash device is busy or ready to accept a new command. This technical note addresses the use of status register bit 5, which indicates the ready/busy status of the NAND Flash device. TN-29-13 02/2010 Technical Note
The Many Flavors of NAND...and More to Come: (PDF 8.03 MB)Keynote for Flash Memory Summit 2009 12/2009 Presentation
The Inconvenient Truths of NAND Flash Memory: (PDF 344.36 KB)Overview of NAND Flash 12/2009 Presentation
Power Requirements for Multi-Bit Per Cell NAND Flash: (PDF 90.65 KB)Technology differences, power consumption considerations 12/2009 Presentation
Overcoming (or Embracing) the Dreaded Single-Source Dilemma: (PDF 241.11 KB)Multisourcing versus single-sourcing 12/2009 Presentation
Optimizing NAND Flash Performance: (PDF 149.28 KB)Improving NAND performance in various applications 12/2009 Presentation
ONFI Standards and What They Mean to Designers: (PDF 166.18 KB)Inconsistencies without ONFI and results with ONFI 12/2009 Presentation
NAND Flash Reliability and Performance - The Software Effect: (PDF 296.15 KB)NAND software 12/2009 Presentation
NAND Flash Consideratons for Consumer Applications: (PDF 700.54 KB)NAND requirements/system reliability in consumer applications 12/2009 Presentation
NAND Flash Architecture and Specification Trends: (PDF 696.58 KB)How to prepare for changes brought on by technology shrinks 12/2009 Presentation
Improving Power Budgeting Estimates in NAND Applications: (PDF 694.29 KB)Measuring Icc with better predictability 12/2009 Presentation
An ONFI Update: (PDF 1007.42 KB)Overview of enhancements and the path to higher performance 12/2009 Presentation
A Closer Look at NAND Flash: (PDF 2.7 MB)Exploring the possibilities of SSDs 12/2009 Presentation
3-Bit/Cell NAND Flash: (PDF 90.87 KB)Architecture, performance, endurance, system requirements, cost advantages, applications 12/2009 Presentation
Flash Memory Technology Direction: (PDF 643.16 KB)This paper explains the trade-offs associated with available disk caching methods, the differences between various types of Flash memory, and the advantages that NAND offers when superior performance is critically important. 12/2009 White Paper
Understanding Signal Integrity: (PDF 1.64 MB)Describes how memory design, test, and verification tools can be used to the greatest advantage, from conception of a new product through end of life TN-00-20 12/2009 Technical Note
Memory Management in NAND Flash Arrays: (PDF 271.42 KB)Describes common NAND Flash memory-management methods for effective use of the NAND Flash memory array TN-29-28 12/2009 Technical Note
IBIS Behavioral Models: (PDF 163.98 KB)Micron has been a member of the IBIS Open Forum for many years and fully supports the IBIS specification. IBIS models for most Micron products are available for download from the Micron Web site. TN-00-07 11/2009 Technical Note
Understanding Quality and Reliability Requirements for Bare Die Applications: (PDF 142.04 KB)Describes the quality and reliability requirements for bare die applications TN-00-14 10/2009 Technical Note
Thinning Considerations for Wafer Products: (PDF 73.58 KB)Information on optimal wafer-thinning processes to meet specific customer requirements TN-00-19 10/2009 Technical Note
ONFI Flyer: (PDF 162.55 KB) 06/2009 Product Flyer
TN-29-37: Comparing 40 and 50-Series SLC NAND Flash Devices: (PDF 728.87 KB)Prior to conversion, Micron recommends that the target design take into account the product data sheet and the specific changes highlighted in this technical note. This Technical note covers the M58A, M59A & M50A products. TN-29-37 01/2009 Technical Note
Wear-Leveling Techniques in NAND Flash Devices: (PDF 268.3 KB)Highlights the importance of wear leveling, explains two wear-leveling techniques, and discusses implementing wear leveling TN-29-42 10/2008 Technical Note
Using COPYBACK Operations to Maintain Data Integrity in NAND Flash Devices: (PDF 101.39 KB)Describes how to use COPYBACK operations in NAND Flash devices TN-29-41 10/2008 Technical Note
Improving NAND Flash Performance Using Two-Plane Command Enabled Micron Devices: (PDF 123.28 KB)Describes the performance benefits of Micron two-plane commands, and provides implementation guidelines for making the best use of two-plane capabilities TN-29-25 09/2008 Technical Note
Booting from Embedded MMC: (PDF 282.02 KB)Describes booting from an embedded ARM processor in the MMC environment TN-29-18 06/2008 Technical Note
Which NAND solution is best for my design?: (PDF 158.84 KB)Micron offers a full line of high-performance memory solutions—from SLC and MLC to Serial NAND, to e•MMC™ and MCPs—for a variety of applications. And we work with chipset vendors, OS designers, and other enablers to ensure that they’re optimized for your design. 11/2007 Webinar
NAND Flash Status Register Response in Cache Programming Operations: (PDF 253.71 KB)Describes status register responses when operating in cache programming modes TN-29-26 06/2007 Technical Note
Boot-from-NAND Using Micron MT28F1G08ABA NAND Flash with the Texas Instruments OMAP 2420 Processor: (PDF 435.55 KB)Describes Boot-from-NAND using Micron MT29F1G08ABA NAND Flash with the Texas Instruments OMAP 2420 processor. TN-29-16 06/2007 Technical Note
Micron® NAND Flash Controller via Xilinx® Spartanâ„¢-3 FPGA: (PDF 872.4 KB)Describes the Micron NAND Flash controller, techniques for interfacing the NAND Flash device with a processor, and use of the Micron glueless interface to interface a processor with NAND Flash memory. TN-29-06 06/2007 Technical Note
Small Block vs. Large Block NAND Devices: (PDF 387.87 KB)Large-block NAND Flash devices offer significant performance increases over their small-block NAND Flash counterparts for READ, PROGRAM, and ERASE operations. TN-29-07 05/2007 Technical Note
NAND Flash Security: (PDF 189.32 KB)Using Micron NAND Flash security features to implement component and code authentication security solutions, designers can protect critical system components and proprietary system software from unwanted attacks and alterations. TN-29-11 05/2007 Technical Note
NAND Flash Performance Increase : (PDF 205.94 KB)Customers using the PAGE READ CACHE MODE operation provided in Micron NAND Flash devices will realize significant performance gains in systems requiring increased data volume at a much faster rate. TN-29-01 05/2007 Technical Note
Monitoring Ready/Busy Status in 2, 4, and 8Gb Micron NAND Flash Devices: (PDF 96.08 KB)Four options for determining the NAND Flash ready/busy device status are presented with detailed explanations of each option. TN-29-13 05/2007 Technical Note
Hamming Codes for NAND Flash Memories: (PDF 229.46 KB)Outlines hamming codes NAND Flash memory TN-29-08 05/2007 Technical Note
ECC Module for Xilinx Spartan-3FPGA: (PDF 997.75 KB)Micron's ECC module was developed and tested using Xilinx(R) Spartan-3 and can be ported to certain other platforms of the user's choosing. TN-29-05 05/2007 Technical Note
FBGA Date Codes: (PDF 22.36 KB)Date codes for FBGA-packaged components 08/2005 Part Numbering Guide
FBGA Decoder: Micron's FBGA Part Marking Decoder makes it easier to understand part marking. Tool
For Products and Support (14)
Title & Description Secure ID# Updated Type
Micron Component and Module Packaging: (PDF 1.35 MB)Explanation of Micron packaging labels and procedures. CSN-16 11/2014 Customer Service Note
Product Marks/Product and Packaging Labels: (PDF 1.58 MB)Explains product part marking, and product and packaging labels. CSN-11 10/2014 Customer Service Note
Shipping Quantities: (PDF 1.22 MB)Provides standard part quantities for shipping. CSN-04 03/2014 Customer Service Note
RMA Procedures for Packaged Product and Bare Die Devices: (PDF 76.22 KB)Outlines standard returned material authorization (RMA) procedures, as well as the differences associated with bare die RMAs. CSN-07 01/2014 Customer Service Note
Wafer Packaging and Packaging Materials: (PDF 591.42 KB)Provides complete shipping and recycling information about each of the materials used for shipping Micron's products. CSN-20 11/2013 Customer Service Note
Thermal Applications: (PDF 246.79 KB)Describes some considerations in thermal applications for Micron memory devices TN-00-08 07/2013 Technical Note
Moisture Absorption in Plastic Packages: (PDF 97.08 KB)Describes shipping procedures for preventing memory devices from absorbing moisture and recommendations for baking devices exposed to excessive moisture TN-00-01 02/2013 Technical Note
Micron BGA Manufacturer's User Guide: (PDF 388.76 KB)Provides information to enable customers to easily integrate both leading-edge and legacy Micron's ball grid array (BGA) packages into their manufacturing processes. It is intended as a set of high-level guidelines and a reference manual describing typical package-related and manufacturing process-flow practices. CSN-33 12/2012 Customer Service Note
Electronic Data Interchange: (PDF 52.45 KB)Describes EDI transmission sets, protocol, and contacts. CSN-06 11/2012 Customer Service Note
PCN/EOL Systems: (PDF 79.21 KB)Explains Micron's product change notification and end-of-life systems. CSN-12 04/2012 Customer Service Note
Lead Frame Package User Guidelines: (PDF 245.66 KB)Discusses Micron's lead-frame package options CSN-30 05/2011 Customer Service Note
ESD Precautions for Die/Wafer Handling and Assembly: (PDF 120.81 KB)Describes the benefits of controlling ESD in the workplace, including higher yields and improved quality and reliability, resulting in reduced manufacturing costs. CSN-24 08/2010 Customer Service Note
Micron KGD Definitions: (PDF 65.52 KB)Describes the testing specifications and parameters for Micron's KGD-C1 and KGD-C2 DRAM die. CSN-22 07/2009 Customer Service Note
Bare Die SiPs and MCMs: (PDF 151.06 KB)Describes design considerations for bare die SiPs and MCMs. CSN-18 04/2009 Customer Service Note

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For MLC NAND (0)
Title & Description Secure ID# Updated Type
For NAND Flash (11)
Title & Description Secure ID# Updated Type
MT29F (1Gb, 2Gb, 4Gb, 8Gb, 16Gb, 32Gb) General Low-Level Driver: (ZIP 595.48 KB)General low-level driver for M60A, M61A, M62B, M68A, M68M, M70M, M71M, M72A, M73A, and M79M family NAND devices. Download the technical note for this driver here. 04/2013 NAND Flash Software
Serialize Function for the SPI Controller: (ZIP 5.55 KB)Provides the serialize function for the serial peripheral interface (SPI) controller for Micron’s serial Flash devices (NAND, NOR, and PCM). 12/2011 NAND Flash Software
M68A, M69A and M60A (1Gb, 2Gb, 4Gb) General Low-Level Driver: (ZIP 12.22 KB)General low-level driver for M68A, M69A, and M60A NAND. 12/2011 NAND Flash Software
Large Page SLC NAND (1Gb, 4Gb) General Low-Level Driver: (ZIP 17.27 KB)General low-level driver for legacy Numonyx large page SLC NAND. Download the technical note for this driver here. 07/2011 NAND Flash Software
BeagleBoard SPI NAND MTD for Linux 2.6.33: (ZIP 9.65 KB)SPI NAND GPL drivers for 50 series NAND. 06/2011 NAND Flash Software
Very Large Page SLC NAND (8Gb) General Low-Level Driver: (ZIP 10.23 KB)General low-level driver for legacy Numonyx very large page SLC NAND. Download the technical note for this driver here. 03/2010 NAND Flash Software
NAND Controller and ECC VHDL: (ZIP 22.47 KB) 02/2010 NAND Flash Software
NAND Binary BCH Code Software: (ZIP 132.93 KB) 02/2010 NAND Flash Software
1-Bit Software ECC: (ZIP 3.26 KB)NAND Flash software driver ECC 12/2009 NAND Flash Software
Small Page SLC NAND (128Mb, 256Mb, 512Mb, 1Gb) General Low-Level Driver: (ZIP 9.59 KB)General low-level driver for legacy Numonyx small page SLC NAND. Download the technical note for this driver here. 11/2009 NAND Flash Software
NAND Flash Low Level Drivers for x16 Devices: (ZIP 15.34 KB) 06/2006 NAND Flash Software
For Products and Support (0)
Title & Description Secure ID# Updated Type

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Do you support small block devices?
Currently, Micron only offers large block devices. For more information, please refer to Technical Note, TN-29-07: Small Block vs. Large Block NAND Devices.
How much ECC do I need to support your devices?
We define our ECC requirement per 512-byte section. MLC NAND devices have a higher ECC requirement than SLC NAND due to the increased number of bits per cell. ECC requirements differ for designs, so consult the device data sheet for the amount of ECC needed.
I am using the correct amount of error correction code (ECC) for the NAND device, but I’m still seeing bit/byte errors in data I read back from the NAND device.
Make sure that you are issuing a READ STATUS command to the NAND device after any type of PROGRAM or ERASE operation. Checking status after a PROGRAM or ERASE operation will report whether the PROGRAM or ERASE operation was successful. If the READ STATUS command reports a failure with a PROGRAM operation, that data should be programmed somewhere else and the block being programmed should be retired. If the READ STATUS command reports a failure with an ERASE operation, that block should also be retired.

NAND Flash FAQs (15)

How do I achieve greater PROGRAM/READ throughput for the NAND device?
To get the maximum PROGRAM/READ throughput for Micron NAND Flash devices, use the PROGRAM and READ CACHE operations. See the NAND device data sheet and our NAND Technical Notes Page for details on how to use these commands.
How is Nvb specified?
Nvb is specified as the minimum number of valid blocks at the end of the P/E cycle spec.
I am seeing a lot of READ DISTURB errors. Can you tell me if there is a problem with your part?
READ disturb occurs when the same data is read repeatedly. By its nature, NAND technology has a very low occurrence of read-disturb errors. But, to mitigate any errors received due to read disturb, we recommend that users refresh the data to reduce the amount of times the same data is read.
I’ve heard that NAND has too many errors to boot from. Is this true?
With ECC, NAND can achieve bit error rates (BER) that are comparable with NOR, which is commonly used as a booting device. Applications that use NAND typically copy the booting code to DRAM and execute from DRAM. For more information, read Tech Note 29-16, which is geared to a specific processor, but the concepts can be applied generally. TN-29-19 is a very useful technical note on the general concepts of NAND.
Should I be marking blocks bad due to READ errors?
When I issue a Read ID command (90h) to a two-die NAND device, I get a device ID back that states it is a one-die NAND device.
In a two-die NAND device, where a single die is on each CE#, the device ID that is returned is per CE# for one die. For example, an 8Gb two-die NAND device with two CE# pins would return a 4Gb device ID on each CE#. See the Read ID section of the NAND device data sheet for more details.
Where can I find additional technical information about Micron NAND devices that is not covered in the device data sheets?
Additional Micron NAND Flash technical information—including details on performance enhancing commands—can be found on the Technical Notes page for NAND.
Where can I find simulation models for NAND Flash devices?
Micron posts Verilog, HSPICE, and IBIS models for NAND devices. To find the right model for your needs, see the appropriate NAND part catalog and select your device to view the available models.
Why am I getting a bit/byte error reading back the information I programmed into the NAND device?
Check that you are using the appropriate amount of error correction code (ECC) for the NAND device. The ECC threshold can be found in the "Error Management" section of the NAND device data sheet. Also ensure that none of the bad blocks marked by the NAND manufacturer (Micron) are used. See the "Error Management" section of the NAND device data sheet for more details on how to search for manufacturer-marked bad blocks.
Why doesn't the NAND Flash device respond correctly to commands issued to it?
Be sure you are issuing a reset command (FFh) to the NAND device after powering on the device. A reset command (FFh) must be issued to each valid chip enable (CE#) of the NAND device before any commands are allowed to be issued to that CE#.
What is a "bank"?
A bank is an array of memory bits. Multiple arrays or banks are contained within a DRAM component. Depending on density, DRAM components may consist of 4 or 8 banks. For example, a bank may consist of 32 million rows, 4 bits across. This would equate to 128 megabits. Four of these banks in a single DRAM component would yield a 512Mb component.
What is the impedance tolerance of the driver in match-impedance mode relative to the expected value base on the perfect reference resistor connected to ZQ pin?
The impedance tolerance of the driver is ±15 percent.
Does thermal information change for IT parts?
Thermal information includes temperature limits and thermal impedance values. Temperature limits do change for IT parts (TC, TJ, and TA), but thermal impedance values (θJA, θJB, and θJC) do not because thermal impedance depends primarily on the package.
My design was based on a specification stating the JTAG was relative to VDD (1.8V), but now we’ve discovered that JTAG is actually relative to VDDQ (1.5V). It’s a fairly significant board spin to change this; what do I risk by leaving the design as-is? I assume that the specification is still for VDDQ + 0.3V = 1.8V, but with CMOS parts there’s no way I can guarantee that it won’t swing past that on transitions.
Your particular board design should not be a cause of major concern. The pins can handle the VDD voltage regardless of the VDDQ voltage.
Should the ECC memory chip share chip select and CKE signals with the other two main memory chips in our point-to-point application?
The ECC chip(s) should share the same CKE and CS# as the other devices because they are accessed as the same piece of data.

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