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Emerging technologies require innovation on a whole new scale. See how we partner closely with our customers to gain unique insights about how we can optimize our memory solutions to enable your innovations—and help you change the world.

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Memory for Automotive

Memory for Automotive

Technology is reshaping the concept of driving. Automakers are developing countless new driver-assistance features and systems. See how Micron’s memory solutions are helping to enable these new supercomputing capabilities.

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About Micron

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For more than 30 years Micron has redefined innovation by designing, developing, and manufacturing some of the world’s most advanced technologies.

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Elpida is Now Micron

Elpida Is Now Micron

With the combined strength of our products, technology, and team members—our customers now have access to the broadest portfolio of best-in-class technology.

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Our RLDRAM roadmap that includes next-generation RLDRAM 3 and extended support for our current-generation RLDRAM 2 memory.

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Unparalleled Bandwidth and Low Latency

Our reduced-latency DRAM (RLDRAM® memory) is a high-performance, high-density memory solution that offers fast SRAM-like random access and outpaces even leading-edge DDR3 for sustained high bandwidth. RLDRAM uses innovative circuit design to minimize the time between the beginning of an access cycle and the instant that the first data is available. These traits make RLDRAM an ideal choice for 10GbE, 40GbE, and 100GbE packet buffering and inspections, and it’s supported on a wide variety of FPGAs and network processor solutions.

Technology Density RoHS Depth Width Voltage Package Pin Count Clock Rate Cycle Time Op. Temp.

RLDRAM 2

See 51 Products
288Mb, 576Mb 5/6, No, Yes 8Mb, 16Mb, 32Mb, 64Mb x9, x18, x36 1.8V uBGA 144-ball 300 MHz, 400 MHz, 533 MHz 1.875ns, 2.5ns, 3.3ns 0C to +95C, -40C to +95C

RLDRAM 3

See 21 Products
576Mb, 1.15Gb Yes 16Mb, 32Mb, 64Mb x18, x36 1.35V FBGA 168-ball 800 MHz, 933 MHz, 1067 MHz 8ns, 10ns, 12ns 0C to +70C, 0C to +95C, -40C to +85C
  • Available in three densities, providing flexibility for many designs
  • Available in wide bus widths with minimal part counts in wide-bus configured systems; common or separate I/O
  • HSTL and SSTL I/O compatibility
  • Increased operating range for optimum functionality in extreme environments
  • Fast random access
  • High sustainable performance
  • Enables clean, high-frequency operation
  • Adds flexibility to board design
  • Essential for testing boards with a high number of components

 

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Partner Ecosystem

Partner Ecosystem

As a leading memory supplier, we’re able to provide our preferred partners with early availability of product samples, regular product and market updates, insights into new memory technologies, and dedicated resources.

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Xilinx/Micron Memory Interface Solution

Next-generation memory solution demo from Xilinx and Micron featuring a Virtex-7 FPGA and a Micron RLDRAM 3 Memory device.

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For RLDRAM Memory (12)
Title & Description Secure ID# Updated Type
RLDRAM 3 Power Calculator: (XLSX 180.51 KB) 07/2014 Power Calculator
Maximize Data Center Performance With Optimized Memory and Storage Solutions: (PDF 725.94 KB) Micron offers a broad portfolio of optimized solutions that deliver improved performance, increased bandwidth with less latency, and improved total cost of ownership. A range of choices—modules for servers and storage arrays, RLDRAM® memory for switch and router packet buffering, SSDs for higher performance and low-power storage, and NOR and NAND Flash for code storage—help businesses scale, simplify, consolidate, and automate, to get the maximum value out of their data centers. 02/2014 Product Flyer
RLDRAM Memory Flyer : (PDF 600.76 KB)Describes the high-bandwidth, low-latency, high-density features of RLDRAM 3 and RLDRAM 2 memory 09/2013 Product Flyer
Networking Solutions Guide: (PDF 240.27 KB)This guide outlines Micron’s various solutions—from DRAM components and modules to NOR and NAND Flash to solid state drives (SSDs)—available for networking applications. 06/2013 Other Documents
High-Performance Memories for Packet Processing: (PDF 1.42 MB) 10/2012 Presentation
Calculating Memory System Power for RLDRAM 2: (PDF 1.77 MB)Details how RLDRAM 2 devices consume power and provides tools to estimate power consumption TN-49-04 10/2012 Technical Note
RLDRAM 2 Clocking Strategies: (PDF 264.17 KB)Addresses the operation of the RLDRAM 2 device outside the specified range of clock periods and the timing changes that occur in this mode of operation TN-49-03 10/2012 Technical Note
Exploring the RLDRAM 2 Feature Set: (PDF 474.43 KB)Outlines the performance-enhancing features offered by RLDRAM 2 architecture TN-49-02 10/2012 Technical Note
RLDRAM 2 Design Guide: (PDF 304.09 KB)Describes the general features of circuit implementations using RLDRAM 2 memory architecture TN-49-01 10/2012 Technical Note
RLDRAM 2 Power Calculator: (XLS 281 KB) 08/2011 Power Calculator
RLDRAM 3 Design Guide: (PDF 723.41 KB)Contains practical recommendations for developing high-performance memory subsystems while ensuring stability for long-term reliable operation of the devices. TN-44-01 08/2011 Technical Note
Leverage Existing RLDRAM 2 and DDR3 PHY to Design in New RLDRAM: (PDF 75.75 KB)RLDRAM 3 and DDR3 PHY features comparison, highlighting how both RLDRAM 2 and DDR3 PHY can be easily leveraged to design in RLDRAM 3. Presentation 05/2011 Presentation
For DRAM (16)
Title & Description Secure ID# Updated Type
DRAM Component Part Numbering System: (PDF 45.91 KB)Part numbering guide for DDR4/DDR3/DDR2/DDR/SDR SDRAM, Mobile LPDRAM, and RLDRAM components 06/2014 Part Numbering Guide
Legacy LPDRAM Part Numbering System: (PDF 114.47 KB)Part numbering guide for legacy LPDDR2 and LPDRR3 PoP and FBGA components 05/2014 Part Numbering Guide
SEMI Wafer Map Format: (PDF 114.26 KB)Micron has adopted the wafer map file format approved by Semiconductor Equipment and Materials International (SEMI). With SEMI formatting, Micron's customers can be confident they will always receive consistent, compatible, reliable map files. TN-00-21 03/2014 Technical Note
HMC Part Numbering System: (PDF 58.88 KB)Part numbering guide for Hybrid Memory Cube 01/2014 Part Numbering Guide
Routing Guidelines for Micron’s HMC-15G-SR: (PDF 3.3 MB)Provides sound methods, proven solutions, and detailed PCB layout guidelines to enable successful designs using Micron’s HMC. TN-43-03 HMC TN-43-03 06/2013 Technical Note
Recommended Soldering Parameters: (PDF 173.37 KB)Defines the recommended soldering techniques and parameters for Micron Technology, Inc., products. TN-00-15 12/2012 Technical Note
Bypass Capacitor Selection for High-Speed Designs: (PDF 481.9 KB)Describes bypass capacitor selection for high-speed designs. TN-00-06 03/2011 Technical Note
Micron Wire-Bonding Techniques: (PDF 66.13 KB)This technical note provides guidance on wire bonding techniques for both nickel-palladium (NiPd) and aluminum (Al) bond pads on Micron products. TN-00-22 11/2010 Technical Note
Uprating of Semiconductors for High-Temperature Applications: (PDF 428.33 KB)Describes the issues associated with temperature uprating and the risks involved in using components and/or systems outside the manufacturer's environmental specifications TN-00-18 05/2010 Technical Note
Accelerate Design Cycles with Simulation Models: (PDF 206.91 KB)Micron supplies the tools and guidelines necessary to verify new designs prior to layout. This technical note discusses software model support, signal integrity optimization, and logic circuit design. TN-00-09 02/2010 Technical Note
The Future of Memory and Storage: (PDF 1.54 MB)Overview of trends for main memory and Flash memory 12/2009 Presentation
Understanding Signal Integrity: (PDF 1.64 MB)Describes how memory design, test, and verification tools can be used to the greatest advantage, from conception of a new product through end of life TN-00-20 12/2009 Technical Note
IBIS Behavioral Models: (PDF 163.98 KB)Micron has been a member of the IBIS Open Forum for many years and fully supports the IBIS specification. IBIS models for most Micron products are available for download from the Micron Web site. TN-00-07 11/2009 Technical Note
Understanding Quality and Reliability Requirements for Bare Die Applications: (PDF 142.04 KB)Describes the quality and reliability requirements for bare die applications TN-00-14 10/2009 Technical Note
FBGA Date Codes: (PDF 22.36 KB)Date codes for FBGA-packaged components 08/2005 Part Numbering Guide
FBGA Decoder: Micron's FBGA Part Marking Decoder makes it easier to understand part marking. Tool
For Products and Support (14)
Title & Description Secure ID# Updated Type
Product Marks/Product and Packaging Labels: (PDF 1.46 MB)Explains product part marking, and product and packaging labels. CSN-11 07/2014 Customer Service Note
Shipping Quantities: (PDF 1.22 MB)Provides standard part quantities for shipping. CSN-04 03/2014 Customer Service Note
RMA Procedures for Packaged Product and Bare Die Devices: (PDF 76.22 KB)Outlines standard returned material authorization (RMA) procedures, as well as the differences associated with bare die RMAs. CSN-07 01/2014 Customer Service Note
Wafer Packaging and Packaging Materials: (PDF 591.42 KB)Provides complete shipping and recycling information about each of the materials used for shipping Micron's products. CSN-20 11/2013 Customer Service Note
Thermal Applications: (PDF 246.79 KB)Describes some considerations in thermal applications for Micron memory devices TN-00-08 07/2013 Technical Note
Moisture Absorption in Plastic Packages: (PDF 97.08 KB)Describes shipping procedures for preventing memory devices from absorbing moisture and recommendations for baking devices exposed to excessive moisture TN-00-01 02/2013 Technical Note
Micron Component and Module Packaging: (PDF 1.41 MB)Explanation of Micron packaging labels and procedures. CSN-16 01/2013 Customer Service Note
Micron BGA Manufacturer's User Guide: (PDF 388.76 KB)Provides information to enable customers to easily integrate both leading-edge and legacy Micron's ball grid array (BGA) packages into their manufacturing processes. It is intended as a set of high-level guidelines and a reference manual describing typical package-related and manufacturing process-flow practices. CSN-33 12/2012 Customer Service Note
Electronic Data Interchange: (PDF 52.45 KB)Describes EDI transmission sets, protocol, and contacts. CSN-06 11/2012 Customer Service Note
PCN/EOL Systems: (PDF 79.21 KB)Explains Micron's product change notification and end-of-life systems. CSN-12 04/2012 Customer Service Note
Lead Frame Package User Guidelines: (PDF 245.66 KB)Discusses Micron's lead-frame package options CSN-30 05/2011 Customer Service Note
ESD Precautions for Die/Wafer Handling and Assembly: (PDF 120.81 KB)Describes the benefits of controlling ESD in the workplace, including higher yields and improved quality and reliability, resulting in reduced manufacturing costs. CSN-24 08/2010 Customer Service Note
Micron KGD Definitions: (PDF 65.52 KB)Describes the testing specifications and parameters for Micron's KGD-C1 and KGD-C2 DRAM die. CSN-22 07/2009 Customer Service Note
Bare Die SiPs and MCMs: (PDF 151.06 KB)Describes design considerations for bare die SiPs and MCMs. CSN-18 04/2009 Customer Service Note

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RLDRAM Memory FAQs (24)

Are CK/CK# and DK/DK# true differential inputs?
Yes, the CK/CK# and DK/DK# input buffers are true differential inputs. Both sets of clocks need to meet the specifications that are defined in the Clock Input Operating Conditions tables in the RLDRAM II memory data sheets.
Are there any new features in RLDRAM 3 not found in earlier generations of the RLDRAM product line?
Yes. Multibank write is a new feature that enables SRAM-like random read capabilities. Managing refresh overhead is now more flexible than ever with the addition of the MULTIBANK REFRESH command. With this command, you can refresh one to four banks simultaneously. We’ve also added a mirror function ball to ease layout of clamshell designs. Depending upon the state of the mirror function ball, the command and address functions are swapped across the y-axis to allow for direct connections through the PCB.
Can 2.5V or 3.3V be directly input to joint test action group (JTAG) pins?
No. The highest operating voltage that can be input to the JTAG pins is VDD + 0.3V as outlined in the TAP DC Electrical Characteristics and Operating Conditions tables in the RLDRAM II data sheets.
Can I connect the “Do Not Use” (DNU) pins to ground (GND)?
Yes. However, when on-die termination (ODT) is enabled, the DNU pins will be connected to VTT. Connecting the DNU pins to GND under these circumstances will cause a substantially larger load on your VTT supply.
Can I reload the mode register after I have been operating with READs and WRITEs on RLDRAM II memory?
Yes, the mode register can be reloaded at any time as long as all timing specifications are met. Burst length must be considered, however. If the burst length is changed, previously written data will be corrupted.
Can RLDRAM II run slower than 175 MHz?
Yes, but the DLL must be turned off. With the DLL turned off, the output data alignment with the CK will shift by about 3–4ns, which works like the outputs of RLDRAM I memory.
Does the 576Mb RLDRAM II device still support 1.8V VDDQ? Is it possible to run at 533 MHz with VDDQ = 1.8V?
It should not be a problem to run at 533 MHz with VDDQ = 1.8V. Micron has run graphics devices at 800 MHz clock at 1.8V.
Does the RLDRAM internally compensate for voltage and temperature changes when bit A8 is not selected HIGH on the RLDRAM II during setting of the mode register?
Yes. When bit A8 of the mode register is HIGH, the user places an external precision resistor between ZQ and VSS to select an output impedance. When bit A8 is LOW, the output impedance is set to 50 ohms (±30 percent). In both cases, however, the RLDRAM device periodically calibrates this impedance to compensate for shifts in voltage and temperature. This calibration is internal to the RLDRAM and does not affect the operation of the RLDRAM.
During initialization, are 2,048 clock cycles really needed between each AUTO REFRESH command?
No. Although it is still outlined in some older data sheet revisions, it is not necessary. During initialization, it is necessary for all eight banks to receive an AUTO REFRESH command tMRSC after the last valid MRS command has been issued. If you sequentially issue AUTO REFRESH commands instead of waiting 2,048 clock cycles between each command, you must perform at least 1,024 NOP commands between the last AUTO REFRESH command and the first valid command in normal operation. Either method will satisfy the requirements of the RLDRAM.
During power-up, I bring VDDQ HIGH before VDD. Will this cause a problem?
The RLDRAM II will not be adversely affected if you bring VDDQ HIGH before VDD. However, you must be aware that when you perform the sequence in this way, the DQs, DM, and all other pins with an output driver will go HIGH instead of tri-stating. These pins will remain HIGH until VDD is at the same level as VDDQ. Care should be taken to avoid bus conflicts during this period.
How can I reset the RLDRAM II device?
RLDRAM II memory can be reset using the MODE REGISTER command. Three MRS commands must be issued on consecutive clock cycles to reset the device properly. If any commands (including NOP commands) are issued between the MRS commands, the device will not be reset.
How is RLDRAM II memory similar to SRAM?
RLDRAM II memory is similar to SRAM in a variety of ways: - Simplified command set: only four commands (READ, WRITE, REFRESH, and MODE REGISTER SELECTION) - Row/columns not apparent: can clock in the full address in one clock cycle (or can be multiplexed like a standard DRAM) - Fast cycle time: 20ns tRC for the 288Mb device and as low as to 15ns tRC for the 576Mb device
I’m seeing substantial jitter on my outputs; what can I do to remedy this?
A number of things can cause jitter on RLDRAM II memory outputs. Read through the questions below to help identify the cause of the jitter. - Is the same amount of jitter seen at the DQs, QKs, and QVLD signal? If so, the jitter may be due to the DLL. The DQs, QKs, and QVLD all use the DLL to clock out their data. Micron can assist with additional debugging to determine whether any parameters are being violated that would cause the DLL to operate improperly.
- Is there jitter on the input clocks? Any jitter on CK/CK# will be transferred to the outputs.
- Does the amount of jitter change substantially with different output data? If it does, phenomena such as ISI, SSO, or crosstalk could be causing the jitter.
- Is the system properly terminated? Because proper termination is dependent on system parameters, simulation is the best way to determine termination requirements. Micron offers several tools and technical notes to assist with termination requirements:
1.“TN-49-02: Exploring the RLDRAM II Feature Set” includes descriptions and examples of data-eyes when using the on-die termination and impedance-matching features.
2. Technical notes TN-46-14 and TN-46-06 do not specifically mention RLDRAM II memory, but they have useful information about termination and techniques to ensure good signal integrity.
3. The RLDRAM Memory Part Catalog contains configuration information for IBIS and HSpice models.
I’m using RLDRAM memory. Is it possible to tie VDD and VDDQ to the same supply?
Yes. You can tie VDD and VDDQ to the same supply.
Is MAX power specified in the data sheet?
Yes, MAX power is specified in the data sheet. Because MAX power is entirely dependent on how the devices are used in a system, the power must be calculated based on information found in the data sheet. In addition to the information found in the data sheet, Micron’s Web site provides a system power calculator to help calculate MAX power based on system use conditions.
Is the tRC timing parameter asynchronous?
No. You must wait the number of clock cycles that correspond with the tRC value for a given configuration before you issue a command to the same bank. For example, if you are using configuration three, you must wait eight clock cycles before you issue another command to the same bank regardless of the operating frequency.
I’ve heard about the new multibank write feature on RLDRAM 3. What exactly is this feature?
Multibank write is a feature that allows for SRAM-like random read access time. Using this feature can reduce RLDRAM 3’s already low tRC (<10ns) by up to 75% during reads. Through the RLDRAM 3 mode register, you can choose to write to one, two, or four banks simultaneously. By storing identical data in multiple banks, the memory controller has the flexibility to determine which bank to read the data from in order to minimize tRC delay.
I’ve heard you’ll be sampling RLDRAM 3 memory in 2011. Do I need to switch to RLDRAM 3?
Not necessarily. While RLDRAM 3 memory offers several performance advantages over RLDRAM 2 memory (it’s twice as fast), we plan to support RLDRAM 2 for a long time. So there’s no urgent need to roll your design. In fact, our die shrink for RLDRAM 2 memory (also coming in 2011) shouldn’t necessitate a design change for existing customers. Contact your Micron representative if you have questions.
Now that you’re introducing RLDRAM 3 technology, should I be concerned about the lifespan for RLDRAM 2 memory?
No. While we’re developing RLDRAM 3 technology we’re also updating the design for RLDRAM 2 memory, transitioning it to our leading 300mm fabs. This process shrink will reduce power consumption and increase performance for the 288Mb product, but most importantly, it will allow us to support RLDRAM 2 memory well into the next decade.
What termination values does DDR3 offer?
DDR3 supports Rtt_Nom values of 120, 60, 40, 30, and 20 ohms. Dynamic ODT (Rtt_Wr) values are 120 and 60 ohms.
When can I get RLDRAM 3 memory?
Early RL 3 samples are available now, with qualified (QS) parts expected in fall 2011, and production beginning at the end of 2011. For more information, request an RLDRAM 3 data sheet.
When I upgrade my system memory from 288Mb to 576Mb RLDRAM II, what design considerations do I need to pay attention to?
The 576Mb RLDRAM II device has been designed as a drop-in solution when upgrading from the 288Mb density. Only one additional address pin is needed to support this upgrade. Also, because of the increase in density, the 576Mb device must be refreshed twice as often as the 288Mb device (131,072 refresh commands for the 576Mb device versus 65,536 refresh commands for the 288Mb device every 32ms). The 576Mb device should meet all other existing timing specifications for a comparable 288Mb speed grade.
Which high-speed transceiver logic (HSTL) class do the RLDRAM II DQs comply with?
The RLDRAM II DQs comply both with HSTL class I and HSTL class II because the DQs’ output impedance can be selected to meet the IOH/IOL requirements of each class. The output impedance is selectable when the MRS bit A8 is set HIGH and an external precision resistor is connected to the ZQ pin. Output impedance values of 25–60 ohms can be chosen when a resistor of five times the desired value is placed between the ZQ ball and VSS. For example, a 300 ohm resistor is required for an output impedance of 60 ohms. With the option of using a 1.8V output voltage and programmable output impedance, the RLDRAM II can also operate in an SSTL environment, although it is not compliant with this standard.
Will I be able to leverage any existing DRAM technology to ease the adoption of RLDRAM 3 in my system?
Yes. Even though RLDRAM 3 is a new architecture, it leverages many features from both DDR3 and RLDRAM 2 to make adoption and integration as easy as possible. The command protocol, addressing, and strobing scheme are the same as RLDRAM 2, while the I/O, AC timing, and read training register very closely resemble those found in DDR3.

DRAM FAQs (8)

Can CKE be tied HIGH throughout SDRAM operation (initialization and normal operation)?
JEDEC does not specify the exact state of CKE during initialization; it is supplier specific. Micron strongly recommends CKE be kept at an LVTTL logic LOW before applying a stable CLK signal. During normal operation, CKE can be tied HIGH. The initial LOW state of CKE prevents parts from receiving an illegal LMR command, which could put the part into an unknown or unexpected state.
Can the SDRAM clock frequency be changed?
Micron SDRAM data sheets require that the clock frequency be constant during access or precharge states (READ, WRITE, tWR, and PRECHARGE commands). At other times frequency should not matter much because there is no DLL in SDRAM however, we do not recommend it. Lowering SDRAM frequency is OK even if you are not doing an LMR and CAS latency change. In case of increasing frequency, ensure tCK and CAS latency specifications are met. In either case, all other data sheet timing specifications should be adhered to.
Is there a recommended lowest working frequency for SDRAM?
Because SDRAM does not have a DLL, there is no recommended lowest frequency. SDRAM parts will work at very low frequencies if all data sheet specifications are met. It is important to maintain a good slew rate, however, since a very slow slew rate will affect setup and hold-time transitions. Also, for operating frequencies of 45 MHz, tCKS = 3.0ns. For more information, see TN-48-09.
What is a "bank"?
A bank is an array of memory bits. Multiple arrays or banks are contained within a DRAM component. Depending on density, DRAM components may consist of 4 or 8 banks. For example, a bank may consist of 32 million rows, 4 bits across. This would equate to 128 megabits. Four of these banks in a single DRAM component would yield a 512Mb component.
What is the impedance tolerance of the driver in match-impedance mode relative to the expected value base on the perfect reference resistor connected to ZQ pin?
The impedance tolerance of the driver is ±15 percent.
Does thermal information change for IT parts?
Thermal information includes temperature limits and thermal impedance values. Temperature limits do change for IT parts (TC, TJ, and TA), but thermal impedance values (θJA, θJB, and θJC) do not because thermal impedance depends primarily on the package.
My design was based on a specification stating the JTAG was relative to VDD (1.8V), but now we’ve discovered that JTAG is actually relative to VDDQ (1.5V). It’s a fairly significant board spin to change this; what do I risk by leaving the design as-is? I assume that the specification is still for VDDQ + 0.3V = 1.8V, but with CMOS parts there’s no way I can guarantee that it won’t swing past that on transitions.
Your particular board design should not be a cause of major concern. The pins can handle the VDD voltage regardless of the VDDQ voltage.
Should the ECC memory chip share chip select and CKE signals with the other two main memory chips in our point-to-point application?
The ECC chip(s) should share the same CKE and CS# as the other devices because they are accessed as the same piece of data.

Products and Support FAQs (1)

Who do I contact if I have questions about my buymicron.com order?
If you have any questions about your order, contact buymicron.com.

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