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Your Innovation, Our Memory

Your Innovation, Our Memory

Emerging technologies require innovation on a whole new scale. See how we partner closely with our customers to gain unique insights about how we can optimize our memory solutions to enable your innovations—and help you change the world.

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Memory for Automotive

Memory for Automotive

Technology is reshaping the concept of driving. Automakers are developing countless new driver-assistance features and systems. See how Micron’s memory solutions are helping to enable these new supercomputing capabilities.

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Elpida Is Now Micron

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All blog posts tagged "DRAM"

Hacking Future Engineers

Micron Foundation   |   March 21, 2014   |   Our Communities

A new STEM-focused event in Boise is receiving a boost from Process Engineer Tristan Andreas, DRAM Designer and Senior Member Technical Staff Wen Li and the Micron Foundation. The inaugural Hackfort, a new component of the Treefort Music Fest, is bringing local technology talent together with three days of talks, panels, demos, presentations, product launches and workshops—including two Hardware Hack sessions led by Andreas on Saturday, March 22. The initial “Circuit-Bending” ...

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Automata Processor: It’s Not Just About Speed and Power Consumption

Paul Dlugosch   |   December 19, 2013   |   All Products

At Supercomputing 13 (SC13), I participated in a discussion panel on the topic of reconfigurable computing.  One recurring theme expressed by the audience was disappointment that the industry is not moving more quickly toward exascale-class performance despite the fact that we have some very powerful CPUs, GPUs, and reconfigurable logic engaged in this effort.  Several panel members pointed to insufficient programmer productivity as the root of this problem.  In other words, ...

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Addressing the tFAW Effect for DDR3

Troy Quick   |   December 17, 2013   |   All Products

Today we announced a solution for an intrinsic DDR3 timing constraint that has been impacting our customers’ system performance. This is great news for networking apps, where tRRD and tFAW timing specifications can restrict much-needed data throughput. Here’s a little background on the issue. Activation delay or tRRD is the amount of time that must elapse between two ACTIVATE commands being issued to different banks.  Four-bank activation window or tFAW is the amount of time i...

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Tags: DRAM, DDR3, Networking

A Look Back at SC13

Richard Murphy   |   December 13, 2013   |   All Products

I attended this year’s Supercomputing Conference (SC13) a few weeks ago and have finally had a chance to sift through all the news announcements, technical sessions, and meeting notes to provide you with a few highlights. Our very own Todd Farrell gave an overview of HMC technology to conference-goers while Micron and Fujitsu announced the integration of our HMC technology into a supercomputer! I think this is a game-changing system design, which will provide flatter, more powerful memory ...

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HMC Arrives Just in Time to Be Your New Standard for Memory Performance: Part 3

Tom Kinsley   |   November 20, 2013   |   All Products

Back again with part 3 of my blog series outlining the features and benefits of Micron’s HMC.  My last post covered HMC’s abstracted memory management, simplified and scalable interface, and superior performance.  Let’s finish up by discussing these additional key features: Uncomplicated Board Layout and Dense Package Our short-reach (SR) HMC device comes in two packages: the four-link, 31mm x 31mm package and the smaller two-link, 16mm x 19.5mm package, which are ea...

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HMC Arrives Just in Time to Be Your New Standard for Memory Performance: Part 2

Tom Kinsley   |   November 14, 2013   |   All Products

In my last post, I touched on some obstacles of traditional memory for system designers and hinted at the reasons why so many companies have selected Hybrid Memory Cube (HMC) as their new standard for memory performance. Here, let’s start to break down some of the key features—including abstracted memory,  unique interface, and superior performance—that make HMC such a breakthrough solution. Abstracted Memory Management and Communication The standard DDR4 data sheet excee...

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HMC Arrives Just in Time to Be Your New Standard for Memory Performance

Tom Kinsley   |   September 25, 2013   |   All Products

Hybrid Memory Cube

Time-to-market and the ability to “tweak” an existing design to achieve that next level of performance are paramount for system architects, board designers, layout engineers, and others responsible for developing high-performance, cost-sensitive, dependable systems. But if you’re reading this, you understand the frustrations and challenges in trying to meet those goals with traditional memory options. The design-to-market time requirements vary greatly by industry but are all ...

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The Memory Innovation Everyone's Been Waiting For

Tom Kinsley   |   July 17, 2013   |   All Products

Folks familiar with technology development know that by the time a working group or a company starts talking publicly about an innovation, it’s really just the tip of the iceberg of what may have been years of thought, problem solving, and development of a solution. All of this forward-looking momentum and investment is ultimately intended to solve problems. And the truth is that no one understands the shortcomings of a technology like the people who work in that technology every day...

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Why Latency Matters

Janene Ellefson   |   April 30, 2013   |   All Products

Latency Matters

When you think about system performance, you have to think latency. In an IT environment, latency affects everything—from efficiency and throughput, to customer satisfaction and operating costs. We are confident that our SSDs can help solve IT latency issues. This video emphasizes the importance of latency using more general, everyday situations.  It’s not often we get to laugh at latency problems. For countless businesses—especially cloud and data center environments&md...

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Optimizing High-speed, Embedded Memory Interface Designs

Steve Durnal   |   March 8, 2013   |   All Products

On March 4, ECN published an article that I wrote where I address considerations in high-speed bus designs for a healthy “data eye.” Read the full article below: Optimizing High-speed, Embedded Memory Interface Designs Designers of energy-efficient, high-speed memory subsystems for small form factor or power-sensitive embedded and wireless products are often making the shift from traditional DDR2/DDR3 to low power (LP) DDR2/DDR3 memory solutions. This is largely in response to the ev...

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