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NAND Flash FAQs

NAND Flash(19)
ClearNAND(6)
How do I achieve greater program/read throughput with a ClearNAND device?
You need to operate at the fastest supported timing mode to get the maximum program/read throughput with Micron ClearNAND Flash. For Standard ClearNAND devices, use multiplane operations wherever possible; for Enhanced ClearNAND devices, issue queued commands via the enhanced command set to improve the device throughput. See the ClearNAND device data sheet for details on how to use these commands.
I am seeing a lot of read disturb errors. Can you tell me if there is a problem with your part?
Read disturb occurs when the same data is read repeatedly. By its nature, NAND technology has a very low occurrence of read disturb errors. However, to mitigate any errors received due to read disturb, we recommend refreshing the data to reduce the amount of times the same data is read.
What types of errors occur with ClearNAND devices compared to traditional NAND?
ClearNAND devices offer additional reliability compared to traditional NAND due to internal ECC, though the same types of errors are present. The host controller can determine whether blocks should be retired or data should be refreshed by monitoring the device status registers following each operation. Additional Micron NAND Flash technical information can be found on the NAND Flash Technical Notes page.
Where can I find simulation models for ClearNAND Flash devices?
Micron posts Verilog, HSpice, and IBIS models for NAND devices. To find the right model for your needs, see the appropriate NAND part catalog and select your device to view the available models.
Why doesn't the ClearNAND Flash device respond correctly to commands issued to it?
Be sure you are issuing a RESET command (FFh) to the NAND device after powering on the device. A RESET command (FFh) must be issued to each valid chip enable (CE#) of the NAND device before any commands are allowed to be issued to that CE#.
Will ClearNAND Flash require new types of controllers?
Standard ClearNAND devices can be used with existing controllers if the controllers support the ONFI 2.3 EZ NAND specification. To take full advantage of the capabilities of our Enhanced ClearNAND device, controllers will need to support the latest ONFI industry standard and incorporate the enhanced command sequences detailed in the device data sheet.
eMMC(17)
What is e.MMC?

Embedded MultiMediaCard (e.MMC) is a NAND Flash-based memory solution defined by JEDEC that comes in a small BGA package. JEDEC defines both the hardware and software, enabling easy customer design-in and the ability to multisource.

What are the benefits of e.MMC?

e.MMC is a fully managed solution (all media management and ECC are handled internally), making NAND technology transitions invisible to the host and providing customers with the ability to reduce their time-to-market and to sustain products longer and more easily.

What does the term "broad market" signify?

Our embedded market e.MMC products are divided into two families: automotive and broad market. This is due to the unique requirements that are required in the automotive market; thus, there is a separate product line supported by Micron’s automotive team. Broad market covers all other market segments such as consumer, gaming, server, networking, industrial, medical, military, etc. Broad market e.MMC includes two sub-families: WT with commercial temperature grade and IT with an extended temperature range.

How can I order samples?

You can order samples through the Micron Sample Center.

Is it necessary to refer to the JEDEC specification as well as to Micron’s data sheet?

Yes, the JEDEC specification has to be read in conjunction with the data sheet. Micron e.MMC complies with the JEDEC standard; hence, Micron's data sheets provide information that is specific only to Micron’s e.MMC devices.

The JEDEC specification (Standard No. 84-A441) is available at: www.jedec.org/sites/default/files/docs/JESD84-A441.pdf

Are simulation models available?

Yes, IBIS models are available for WT and IT products (JEDEC 153-/169-ball and 100-ball); functional models (such as Verilog) are under evaluation.

What is the e.MMC offering for industrial applications?
Micron is offering an extensive number of solutions for industrial customers, such as five densities and JEDEC-standard BGA 153-/169-ball and custom 100-ball packaging. All of these products will operate in the extended temperature range of -40° to 85°C.
What are the advantages of 100-ball IT e.MMC?

Micron’s 100-ball e.MMC BGA package features a 1.0mm ball pitch for board routing simplification (saving PCB costs) and improved board-level reliability (temp cycling). This solution is particularly attractive to automotive, industrial, and networking market segments. See the following table for additional benefits.

Features of 100-ball e.MMC

Benefits

Large 1.0mm ball pitch

  • Allows for low-cost PCB trace/space designs
  • Simplifies PCB routing
  • Enables a reduction in the number of PCB layers
  • Reduces costs via a lower drill size
  • Lower DAR (drill aspect ratio) for better PCB yields
  • Allows for wider traces for better thermal dissipation

Large 0.45mm nominal ball diameter

  • Provides high PCB board-level reliability
  • Improves surface-mount yields (vs. smaller ball packages)
  • Provides better thermal dissipation

Low ball count (compared to 153-ball e.MMC JEDEC-standard)

  • Allows for easier, low-cost PCB routing
  • Reduces package and PCB costs

100-ball pattern contains 12 mechanical support balls (3 in each corner)

  • Provides excellent PCB board-level reliability
  • Allows for flexible “large package size” variations

Flexible ball-out design

  • Allows for future e.MMC feature upgrades and next-generation technology
Is Micron the only provider of 100-ball IT e.MMC?

Greenliant Systems offers pin-compatible 100-ball IT e.MMC for those customers requiring a second source. The NANDrive GLS85VM e.MMC product family supports the JEDEC 4.4 standard and operates at full industrial temperature of -40°C to +85°C. The product line is targeted for industrial and the broad market. For further information and support contact: www.Greenliant.com.

Does Micron's e.MMC support SPI mode?

Micron’s e.MMC 4.41 products are compliant to the JEDEC standard. JEDEC removed this feature when introducing the e.MMC 4.3 specification; therefore, SPI mode is not supported. 

Is v. 4.41 e.MMC functionality backward-compatible to v. 4.3?
Yes, v. 4.41 functionality is backward-compatible with v. 4.3; a v. 4.41 e.MMC device will work with a v. 4.3 or v. 4.4 MMC host. The v. 4.41 devices support additional features such as boot and RPMB partitions, high-priority interrupt, background operation, write reliability, and enhanced reliable write.
How can I migrate from Micron e.MMC 4.4 to 4.41?

Micron has EOL’d its e.MMC 4.4 offering. Refer to your AE for support. A dedicated technical note “TN-FC-08: Migrating from Micron v. 4.4 e.MMC to 4.41 e.MMC” is available for review.

Is it possible to perform a system boot from e.MMC?

Yes, e.MMC provides two boot partitions to provide fast access to boot code for improved system boot time. Booting from boot partitions can provide access to stored data in ~50ms, whereas booting from the user area can take hundreds of milliseconds. However, in order to utilize the boot partitions, the chipset must be able to support booting from the boot partition. Check with your chipset vendor to understand if booting from the e.MMC boot partitions is supported.

For more information, refer to “TN-FC-06: Booting from Embedded MMC - JEDEC 4.41.

Does Micron e.MMC support power-loss protection?

Yes, ESG e.MMC devices support static data protection. Devices are shipped from Micron factories as COMBO with a configuration optimized for best write performance. Customers can reconfigure the devices to protect static (previously written) data if there is power loss during a write operation.

What are the enhanced technology features mentioned in JEDEC specification, and what are the benefits?

A part or all of the MLC user space can be configured as pseudo-SLC. The partition offers better reliability, endurance, and performance compared to MLC NAND.

Can I set up partitions within e.MMC to suit different usage models?

The e.MMC specification allows customers to configure the user data area into a maximum of four separate partitions that can each be configured as MLC (default) or enhanced mode (pSLC). Enhanced mode provides better reliability in exchange for twice the space as MLC.

For more information refer to “TN-52-07: e.MMC Partitioning.

What is the required software support for e.MMC?

e.MMC drivers are generally available on the market due to the fact that it is an industry-standard product.

The e.MMC v. 4.41 standard provides performance, security, and reliability features such as high-priority interrupt and secure erase. These features, such as secure erase and secure trim, require software support from the file system beyond the driver, without which the application call will not reach the storage media via the file system.

Linux supports e.MMC and allows the integration within its subsystems and the Android file system. The advanced features introduced by the JEDEC specification have been supported by patches initially and have only very recently been included in the kernel. See Micron technical note TN-52-05 for details about e.MMC Linux enablement for new features by JEDEC 4.4–4.41.

Proprietary software solutions are available on the market as well.

eUSB(7)
What is eUSB?
The embedded universal serial bus (eUSB) is a NAND flash-based memory solution that is compliant with the USB industry standards. USB is a widely adopted interface used across multiple platforms and operating systems, providing a low-cost, efficient data transfer solution for current applications and beyond.
What are the benefits of eUSB?

eUSB is a fully managed solution that utilizes NAND memory and, through an onboard controller, internally handles all media management and ECC control. The eUSB provides customers with a complete storage solution that easily integrates into their system and, in turn, fuels a reduced time to market.

Using native SLC NAND memory, combined with a rich set of management features such as global wear leveling and dynamic data refresh, eUSB offers a superior combination of performance and reliability.

How does the eUSB attach to my system board?
The eUSB device has a 10-pin (2x5) USB female connector compatible with the industry-standard 10-pin connector found on most motherboards. A mounting hole (connected directly to internal ground) is also provided on the PCB to ensure a stable connection to the system board.  Additional holes in the PC board, utilized during manufacturing for de-paneling, can also be used as additional mounting locations if required.
Can I use the eUSB as a boot device?
Yes. Micron’s eUSB can be used as the operating system boot and main storage device. However, the application’s BIOS must support the boot mode feature, which should not be a concern for most systems that were manufactured in the last five years and support USB 2.0. In either the main storage or boot mode, the eUSB should be recognized as a fixed hard drive in the system.
Does Micron offer the eUSB with a 3.3V option?
Yes. Please check the part catalog for Micron’s current eUSB offerings.
Does Micron provide a way for me to determine the useful life remaining on the device?
Our latest generation eU500, eUSB 3.1 products do provide a method to extract relevant lifetime data through the use of SMART commands. However, previous generations of eUSB products do not support a runtime method to collect lifetime data.
Is eU500 (eUSB 3.1) fully backward compatible with e230 (eUSB 2.0)?
Yes. Micron’s latest generation eU500 eUSB 3.1 products are backward compliant with the USB 2.0 protocol. The eU500 family also supports the same form factor, voltages and connector offerings as the previous generation e230. Please check the part catalog for Micron’s current eUSB offerings.
3D NAND(4)
Why is 3D NAND necessary?
Planar NAND flash memory is nearing its practical scaling limits, which poses challenges for the memory industry.  Industry innovation requires state-of-the-art NAND technology that scales with higher densities and lower cost per bit. 3D NAND allows flash storage solutions to continue aligning with Moore’s Law, bringing significant improvements in density while lowering the cost of NAND flash.
What sets apart this 3D NAND from other offerings in the industry?

The 3D NAND technology developed by Intel and Micron offers significant improvements in density and cost, and it’s the first 3D NAND to use floating gate cells.  This 3D NAND enables flash devices with three times higher capacity than other planar NAND die in production, and the first generation is architected to achieve better cost efficiencies than planar NAND. There are also various features that will improve latency, increase endurance and make system integration easier.

Micron’s 3D is a “smarter” NAND technology. What do you mean?
We have integrated various features to deliver improved performance and new functionality, including new programming algorithms and power management modes that help make system integration easier. See FortisFlash to learn more about these features.
What are the details of your cell and process technology for 3D NAND?
The new 3D NAND technology uses floating gate cells and stacks flash cells vertically in 32 layers to achieve 256Gb multilevel cell (MLC) and 384Gb triple-level cell (TLC) die that fit within a standard package.
Do you support small block devices?
Currently, Micron only offers large block devices. For more information, please refer to Technical Note, TN-29-07: Small Block vs. Large Block NAND Devices.
How do I achieve greater PROGRAM/READ throughput for the NAND device?
To get the maximum PROGRAM/READ throughput for Micron NAND Flash devices, use the PROGRAM and READ CACHE operations. See the NAND device data sheet and our NAND Technical Notes Page for details on how to use these commands.
How is High-Speed NAND different from traditional NAND?
High-Speed NAND can read data at speeds up to 200 megabytes per second (MB/s) and can write data at speeds up to 100 MB/s. These speeds are achieved by leveraging the new ONFI 2.0 interface specification and a four-plane architecture with higher clock speeds. In comparison, conventional SLC NAND is limited to 40 MB/s for reading data and less than 20 MB/s for writing data. To maximize the performance benefits of High-Speed NAND, users must use the new ONFI 2.0 synchronous interface standard.
How is Nvb specified?
Nvb is specified as the minimum number of valid blocks at the end of the P/E cycle spec.
How much ECC do I need to support your devices?
We define our ECC requirement per 512-byte section. MLC NAND devices have a higher ECC requirement than SLC NAND due to the increased number of bits per cell. ECC requirements differ for designs, so consult the device data sheet for the amount of ECC needed.
I am seeing a lot of READ DISTURB errors. Can you tell me if there is a problem with your part?
READ disturb occurs when the same data is read repeatedly. By its nature, NAND technology has a very low occurrence of read-disturb errors. But, to mitigate any errors received due to read disturb, we recommend that users refresh the data to reduce the amount of times the same data is read.
I am using the correct amount of error correction code (ECC) for the NAND device, but I’m still seeing bit/byte errors in data I read back from the NAND device.
Make sure that you are issuing a READ STATUS command to the NAND device after any type of PROGRAM or ERASE operation. Checking status after a PROGRAM or ERASE operation will report whether the PROGRAM or ERASE operation was successful. If the READ STATUS command reports a failure with a PROGRAM operation, that data should be programmed somewhere else and the block being programmed should be retired. If the READ STATUS command reports a failure with an ERASE operation, that block should also be retired.
I’ve heard that NAND has too many errors to boot from. Is this true?
With ECC, NAND can achieve bit error rates (BER) that are comparable with NOR, which is commonly used as a booting device. Applications that use NAND typically copy the booting code to DRAM and execute from DRAM. For more information, read Tech Note 29-16, which is geared to a specific processor, but the concepts can be applied generally. TN-29-19 is a very useful technical note on the general concepts of NAND.
Should I be marking blocks bad due to READ errors?
Yes.
What NAND parts have been validated with the OMAP35x?
Micron works closely with Texas Instruments (TI) to validate and optimize our parts for the OMAP35x processors. As we work with the OMAP35x team, the list of validated memory devices expands frequently. For the most current information, contact your local Micron support.
When I issue a Read ID command (90h) to a two-die NAND device, I get a device ID back that states it is a one-die NAND device.
In a two-die NAND device, where a single die is on each CE#, the device ID that is returned is per CE# for one die. For example, an 8Gb two-die NAND device with two CE# pins would return a 4Gb device ID on each CE#. See the Read ID section of the NAND device data sheet for more details.
Where can I find additional technical information about Micron NAND devices that is not covered in the device data sheets?
Additional Micron NAND Flash technical information—including details on performance enhancing commands—can be found on the Technical Notes page for NAND.
Where can I find simulation models for NAND Flash devices?
Micron posts Verilog, HSPICE, and IBIS models for NAND devices. To find the right model for your needs, see the appropriate NAND part catalog and select your device to view the available models.
Why am I getting a bit/byte error reading back the information I programmed into the NAND device?
Check that you are using the appropriate amount of error correction code (ECC) for the NAND device. The ECC threshold can be found in the "Error Management" section of the NAND device data sheet. Also ensure that none of the bad blocks marked by the NAND manufacturer (Micron) are used. See the "Error Management" section of the NAND device data sheet for more details on how to search for manufacturer-marked bad blocks.
Why doesn't the NAND Flash device respond correctly to commands issued to it?
Be sure you are issuing a reset command (FFh) to the NAND device after powering on the device. A reset command (FFh) must be issued to each valid chip enable (CE#) of the NAND device before any commands are allowed to be issued to that CE#.