The high-performance, on-package memory found in Knights Landing leverages the fundamental DRAM and stacking technologies also found in Micron’s HMC products.
While leveraging the same fundamental technology benefits of HMC, this high-performance on-package memory has been optimized for integration into Knights Landing platforms.
Micron and Intel have been collaborating on methods to break down the memory wall for years. The teams demonstrated early success at IDF 2011 where Micron’s HMC Gen1 device and an Intel memory interface targeted at many-core CPUs provided a sneak peek at the future of memory.
Both Micron and Intel believe that high-performance, on-package memory will play a significant role in multi-core CPU architectures now and in the future.
No, this memory solution has been developed specifically for Intel’s Knights Landing.
This memory solution was developed with the intent of being integrated into the Knights Landing platform; there is no plan for standardization at this time.
Just like HMC, high-performance, on-package memory provides unprecedented levels of memory bandwidth with a fraction of the energy and footprint of existing memory technologies along with the RAS capabilities required by HPC systems.
The HMC Consortium (HMCC) is devoted to developing and driving open-standard interface and protocol platforms.