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Knights Landing FAQs

Hybrid Memory Cube
Knights Landing(8)
What is Micron announcing regarding Intel’s Knights Landing next-generation CPU architecture?

The high-performance, on-package memory found in Knights Landing leverages the fundamental DRAM and stacking technologies also found in Micron’s HMC products.

Is this high-performance, on-package memory the same as HMC?

While leveraging the same fundamental technology benefits of HMC, this high-performance on-package memory has been optimized for integration into Knights Landing platforms.

How have Intel and Micron collaborated to bring this solution to fruition?

Micron and Intel have been collaborating on methods to break down the memory wall for years. The teams demonstrated early success at IDF 2011 where Micron’s HMC Gen1 device and an Intel memory interface targeted at many-core CPUs provided a sneak peek at the future of memory.

Are there plans to use this high-performance, on-package memory on other (future) Intel platforms?

Both Micron and Intel believe that high-performance, on-package memory will play a significant role in multi-core CPU architectures now and in the future.

Will this high-performance, on-package memory be available to other customers?

No, this memory solution has been developed specifically for Intel’s Knights Landing.

Will Intel standardize high-performance, on-package memory?

This memory solution was developed with the intent of being integrated into the Knights Landing platform; there is no plan for standardization at this time.

What is the value that high-performance, on-package memory brings to Knights Landing?

Just like HMC, high-performance, on-package memory provides unprecedented levels of memory bandwidth with a fraction of the energy and footprint of existing memory technologies along with the RAS capabilities required by HPC systems.

How does high-performance, on-package memory differ from what is being developed within the HMC Consortium?

The HMC Consortium (HMCC) is devoted to developing and driving open-standard interface and protocol platforms.