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Hybrid Memory Cube FAQs

Hybrid Memory Cube(1)
Short-Reach HMC(8)
What problem does HMC solve?

Over time, memory bandwidth became a severe bottleneck to optimal system performance. Conventional memory technologies were struggling to keep pace with the increasing performance demands of the latest microprocessor and application-specific integrated circuit (ASIC) roadmaps. Microprocessor and ASIC enablers are doubling cores and threads per core to greatly increase performance and workload capabilities. They are doing this by distributing work sets into smaller blocks among an increasing number of work elements (cores). Multiple compute elements per processor require an increasing amount of memory accesses per element. The term “memory wall” has been used to describe this dilemma. With bandwidth performance levels that break through the memory wall, HMC enables greater performance for next-generation computing and high-speed networking systems.

What are the measurable benefits of HMC?
  • Increased Bandwidth − A single HMC unit can provide up to 160GB/s bandwidth
  • Reduced Latency – With vastly more responders built into HMC, we expect lower queue delays and higher bank availability, which will provide a substantial system latency reduction—a key advantage in networking system design.
  • Power Efficiency − HMC’s revolutionary architecture enables greater power efficiency and energy savings, utilizing up to 70% less energy per bit than DDR3-1333 DRAM technologies.
  • Smaller Physical Footprint − HMC’s stacked architecture uses nearly 90% less physical space than today’s RDIMMs.
  • Pliable to Multiple Platforms − Logic layer flexibility enables HMC to be tailored to multiple platforms and applications.
  • Ultra Reliability HMC delivers greater resilience and field reparability with a new paradigm of system-level, advanced reliability, availability, and serviceability (RAS) features that include embedded error-checking and correction capabilities.
  • Abstracted Memory − Designers can leverage HMC’s revolutionary features and performance without having to interface with complex memory parameters. HMC manages error correction, resiliency, refresh, and other parameters exacerbated by memory process variation.
What does the implementation of HMC look like?

HMC is tightly coupled with CPUs, GPUs, and ASICS in direct point-to-point configurations where HMC performance is essential to system performance. The result is low pin counts with easy board routing in straightforward designs. In systems that require higher density, HMC supports chaining and half-width link configurations to keep the host pin counts down and the designs simple.

What industries/segments do you anticipate will be affected the most?

Any applications where high performance and energy efficiency are critical will be dramatically affected by this technology. For example, the challenge for network systems to maintain line speed performance provides an excellent opportunity for HMC. System developers recognize that a memory bottleneck exists for system development beyond 100Gb and are actively looking for high-performance memory applications for data packet processing and data packet buffering or storage.

The high-performance computing segment is also hitting the memory wall. While processor roadmaps attempt to keep pace through core and thread doubling, core and thread count has not been matched with adequate memory performance. The second major challenge for high-performance computing is energy consumption. Higher-performance processing and exponential bit growth requirements are pushing data centers beyond practical limits for managing power and total cost of ownership. A more energy-efficient solution is desperately needed.
What is the HMCC and what are its goals?

The Hybrid Memory Cube Consortium (HMCC) is a working group made up of industry leaders who build, design in, or enable HMC technology. The goal of the HMCC is to define industry-adoptable HMC interfaces and to facilitate the integration of HMC into a wide variety of applications that enable developers, manufacturers, and enablers to leverage this revolutionary technology.

What does the HMCC specification cover?

The specification includes two PHY definitions and a common protocol. The short-reach (SR) PHY is designed for applications needing channel lengths up to 8 inches, and the ultra short-reach (USR) PHY is intended for applications requiring very short and power-efficient channels with lengths from 1 to 2 inches.

Where can the HMCC specification be accessed?

The HMCC specification is publically available on hybridmemorycube.org.

What Micron parts are available?

Our 2GB HMC device composed of a stack of four 4Gb DRAM die is available. HMC is designed using the HMCC’s short-reach (SR) PHY definition and is available in a 31mm x 31mm package offering four links with full 160 GB/s bandwidth.