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RLDRAM FAQs

RLDRAM(23)
Are CK/CK# and DK/DK# true differential inputs?
Yes, the CK/CK# and DK/DK# input buffers are true differential inputs. Both sets of clocks need to meet the specifications that are defined in the Clock Input Operating Conditions tables in the RLDRAM II memory data sheets.
Are there any new features in RLDRAM 3 not found in earlier generations of the RLDRAM product line?
Yes. Multibank write is a new feature that enables SRAM-like random read capabilities. Managing refresh overhead is now more flexible than ever with the addition of the MULTIBANK REFRESH command. With this command, you can refresh one to four banks simultaneously. We’ve also added a mirror function ball to ease layout of clamshell designs. Depending upon the state of the mirror function ball, the command and address functions are swapped across the y-axis to allow for direct connections through the PCB.
Can 2.5V or 3.3V be directly input to joint test action group (JTAG) pins?
No. The highest operating voltage that can be input to the JTAG pins is VDD + 0.3V as outlined in the TAP DC Electrical Characteristics and Operating Conditions tables in the RLDRAM II data sheets.
Can I connect the “Do Not Use” (DNU) pins to ground (GND)?
Yes. However, when on-die termination (ODT) is enabled, the DNU pins will be connected to VTT. Connecting the DNU pins to GND under these circumstances will cause a substantially larger load on your VTT supply.
Can I reload the mode register after I have been operating with READs and WRITEs on RLDRAM II memory?
Yes, the mode register can be reloaded at any time as long as all timing specifications are met. Burst length must be considered, however. If the burst length is changed, previously written data will be corrupted.
Can RLDRAM II run slower than 175 MHz?
Yes, but the DLL must be turned off. With the DLL turned off, the output data alignment with the CK will shift by about 3–4ns, which works like the outputs of RLDRAM I memory.
Does the 576Mb RLDRAM II device still support 1.8V VDDQ? Is it possible to run at 533 MHz with VDDQ = 1.8V?
It should not be a problem to run at 533 MHz with VDDQ = 1.8V. Micron has run graphics devices at 800 MHz clock at 1.8V.
Does the RLDRAM internally compensate for voltage and temperature changes when bit A8 is not selected HIGH on the RLDRAM II during setting of the mode register?
Yes. When bit A8 of the mode register is HIGH, the user places an external precision resistor between ZQ and VSS to select an output impedance. When bit A8 is LOW, the output impedance is set to 50 ohms (±30 percent). In both cases, however, the RLDRAM device periodically calibrates this impedance to compensate for shifts in voltage and temperature. This calibration is internal to the RLDRAM and does not affect the operation of the RLDRAM.
During initialization, are 2,048 clock cycles really needed between each AUTO REFRESH command?
No. Although it is still outlined in some older data sheet revisions, it is not necessary. During initialization, it is necessary for all eight banks to receive an AUTO REFRESH command tMRSC after the last valid MRS command has been issued. If you sequentially issue AUTO REFRESH commands instead of waiting 2,048 clock cycles between each command, you must perform at least 1,024 NOP commands between the last AUTO REFRESH command and the first valid command in normal operation. Either method will satisfy the requirements of the RLDRAM.
During power-up, I bring VDDQ HIGH before VDD. Will this cause a problem?
The RLDRAM II will not be adversely affected if you bring VDDQ HIGH before VDD. However, you must be aware that when you perform the sequence in this way, the DQs, DM, and all other pins with an output driver will go HIGH instead of tri-stating. These pins will remain HIGH until VDD is at the same level as VDDQ. Care should be taken to avoid bus conflicts during this period.
How can I reset the RLDRAM II device?
RLDRAM II memory can be reset using the MODE REGISTER command. Three MRS commands must be issued on consecutive clock cycles to reset the device properly. If any commands (including NOP commands) are issued between the MRS commands, the device will not be reset.
How is RLDRAM II memory similar to SRAM?
RLDRAM II memory is similar to SRAM in a variety of ways: - Simplified command set: only four commands (READ, WRITE, REFRESH, and MODE REGISTER SELECTION) - Row/columns not apparent: can clock in the full address in one clock cycle (or can be multiplexed like a standard DRAM) - Fast cycle time: 20ns tRC for the 288Mb device and as low as to 15ns tRC for the 576Mb device
I’m seeing substantial jitter on my outputs; what can I do to remedy this?
A number of things can cause jitter on RLDRAM II memory outputs. Read through the questions below to help identify the cause of the jitter. - Is the same amount of jitter seen at the DQs, QKs, and QVLD signal? If so, the jitter may be due to the DLL. The DQs, QKs, and QVLD all use the DLL to clock out their data. Micron can assist with additional debugging to determine whether any parameters are being violated that would cause the DLL to operate improperly.
- Is there jitter on the input clocks? Any jitter on CK/CK# will be transferred to the outputs.
- Does the amount of jitter change substantially with different output data? If it does, phenomena such as ISI, SSO, or crosstalk could be causing the jitter.
- Is the system properly terminated? Because proper termination is dependent on system parameters, simulation is the best way to determine termination requirements. Micron offers several tools and technical notes to assist with termination requirements:
1.“TN-49-02: Exploring the RLDRAM II Feature Set” includes descriptions and examples of data-eyes when using the on-die termination and impedance-matching features.
2. Technical notes TN-46-14 and TN-46-06 do not specifically mention RLDRAM II memory, but they have useful information about termination and techniques to ensure good signal integrity.
3. The RLDRAM Memory Part Catalog contains configuration information for IBIS and HSpice models.
I’m using RLDRAM memory. Is it possible to tie VDD and VDDQ to the same supply?
Yes. You can tie VDD and VDDQ to the same supply.
Is MAX power specified in the data sheet?
Yes, MAX power is specified in the data sheet. Because MAX power is entirely dependent on how the devices are used in a system, the power must be calculated based on information found in the data sheet. In addition to the information found in the data sheet, Micron’s Web site provides a system power calculator to help calculate MAX power based on system use conditions.
Is the tRC timing parameter asynchronous?
No. You must wait the number of clock cycles that correspond with the tRC value for a given configuration before you issue a command to the same bank. For example, if you are using configuration three, you must wait eight clock cycles before you issue another command to the same bank regardless of the operating frequency.
I’ve heard about the new multibank write feature on RLDRAM 3. What exactly is this feature?
Multibank write is a feature that allows for SRAM-like random read access time. Using this feature can reduce RLDRAM 3’s already low tRC (<10ns) by up to 75% during reads. Through the RLDRAM 3 mode register, you can choose to write to one, two, or four banks simultaneously. By storing identical data in multiple banks, the memory controller has the flexibility to determine which bank to read the data from in order to minimize tRC delay.
I’ve heard you’ll be sampling RLDRAM 3 memory in 2011. Do I need to switch to RLDRAM 3?
Not necessarily. While RLDRAM 3 memory offers several performance advantages over RLDRAM 2 memory (it’s twice as fast), we plan to support RLDRAM 2 for a long time. So there’s no urgent need to roll your design. In fact, our die shrink for RLDRAM 2 memory (also coming in 2011) shouldn’t necessitate a design change for existing customers. Contact your Micron representative if you have questions.
Now that you’re introducing RLDRAM 3 technology, should I be concerned about the lifespan for RLDRAM 2 memory?
No. While we’re developing RLDRAM 3 technology we’re also updating the design for RLDRAM 2 memory, transitioning it to our leading 300mm fabs. This process shrink will reduce power consumption and increase performance for the 288Mb product, but most importantly, it will allow us to support RLDRAM 2 memory well into the next decade.
When can I get RLDRAM 3 memory?
Early RL 3 samples are available now, with qualified (QS) parts expected in fall 2011, and production beginning at the end of 2011. For more information, request an RLDRAM 3 data sheet.
When I upgrade my system memory from 288Mb to 576Mb RLDRAM II, what design considerations do I need to pay attention to?
The 576Mb RLDRAM II device has been designed as a drop-in solution when upgrading from the 288Mb density. Only one additional address pin is needed to support this upgrade. Also, because of the increase in density, the 576Mb device must be refreshed twice as often as the 288Mb device (131,072 refresh commands for the 576Mb device versus 65,536 refresh commands for the 288Mb device every 32ms). The 576Mb device should meet all other existing timing specifications for a comparable 288Mb speed grade.
Which high-speed transceiver logic (HSTL) class do the RLDRAM II DQs comply with?
The RLDRAM II DQs comply both with HSTL class I and HSTL class II because the DQs’ output impedance can be selected to meet the IOH/IOL requirements of each class. The output impedance is selectable when the MRS bit A8 is set HIGH and an external precision resistor is connected to the ZQ pin. Output impedance values of 25–60 ohms can be chosen when a resistor of five times the desired value is placed between the ZQ ball and VSS. For example, a 300 ohm resistor is required for an output impedance of 60 ohms. With the option of using a 1.8V output voltage and programmable output impedance, the RLDRAM II can also operate in an SSTL environment, although it is not compliant with this standard.
Will I be able to leverage any existing DRAM technology to ease the adoption of RLDRAM 3 in my system?
Yes. Even though RLDRAM 3 is a new architecture, it leverages many features from both DDR3 and RLDRAM 2 to make adoption and integration as easy as possible. The command protocol, addressing, and strobing scheme are the same as RLDRAM 2, while the I/O, AC timing, and read training register very closely resemble those found in DDR3.