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DDR3 SDRAM FAQs

DDR3 SDRAM(16)
Are the DDR3 voltages backward compatible?

Yes, all of our 1.35V parts are backward compatible with 1.5V.

Can I run Micron’s DDR3 memory at clock speeds slower than 300 MHz?
Yes. Micron supports the optional feature to disable the DLL. This feature allows the DRAM to operate at frequencies slower than 125 MHz. A minimum clock rate is not specified, but the timing still must satisfy the refresh interval (tREFI). When operating in DLL disable mode, special conditions apply: - no support of on-die termination (ODT); ODT must be disabled or turned off - both CL and CWL must be equal to 6 - data out is no longer edge-aligned to the clock and read latency will be AL + CL - 1 tCK
How do I determine my CAS WRITE latency (CWL)?
In DDR3, only one CWL is valid for a given clock frequency range. - tCKavg = 2.5ns to <3.3ns, CWL = 5 - tCKavg = 1.875ns to <2.5ns, CWL = 6 - tCKavg = 1.5ns to <1.875ns, CWL = 7 - tCKavg = 1.25ns to <1.5ns, CWL = 8
How do I determine the amount of time between ZQCS commands?
Each ZQCS command can correct a minimum of 0.5 percent impedance error within 64 clocks. To calculate the ZQCS interval, use the following formula: ZQCS Interval =ZQCorrection (Tsens x Tdriftrate) + (VSens x Vdriftrate) For the sensitivities, use the MAX number from the ODT voltage and temperature sensitivity table in the component specification. Drift rates will vary from system to system. ZQCorrection equals 0.5%/64 clocks.
What component densities are available?
JEDEC has defined DDR3 densities of 512Mb–8Gb; Micron plans to support 1Gb through 4Gb.
What is burst chop?
Due to DDR3's use of the 8n-prefetch architecture, a true burst of 4 is not possible with most designs. Burst chop mode (BC4) is unique to DDR3. In this mode, the last 4 bits of the burst are essentially masked. Timing in BC4 cannot be treated like a true BL4. For READ-to-WRITE, select WRITE-to-READ, and select WRITE-to-PRECHARGE transitions, the system can achieve clock savings in the BC4 mode. While doing READ-to-READ or WRITE-to-WRITE transitions, timing must be treated like BL8; no clock savings will be realized.
What is Dynamic ODT?
Dynamic ODT (Rtt_WR) enables the DRAM to change termination values during a WRITE without having to perform a MODE REGISTER SET command. When Rtt_Wr and Rtt_Nom are both enabled, the DRAM will change termination values from Rtt_Nom to Rtt_Wr at the beginning of the WRITE burst. Once the burst is complete, the termination will be changed back to the Rtt_Nom value. Rtt_Wr can be used independently of Rtt_Nom, but termination will be on WRITEs only.
What is the difference between the ZQCL and ZQCS commands?
ZQCL stands for ZQ calibration long. This command must be issued during the power-up and initialization sequence and requires 512 clocks to complete. After power-up and initialization, the command can be issued any time the DRAM is idle. These subsequent commands only require 246 clocks. This command is used when there is more impedance error correction required than a ZQCS can provide. ZQCS stands for ZQ calibration short. This command can be performed any time the DRAM is idle. One ZQCS can correct a minimum of 0.5 percent impedance error and requires 64 clocks.
What is the "MPR"?
MPR is a multi-purpose register. It is a specialized register designed to allow predefined data to be read out of the DRAM. Data is one bit wide and is output on a prime DQ. For Micron DDR3 parts, the prime DQs are DQ0 for x4/x8 and DQ0/DQ8 for x16. Two locations in the MPR are defined. One allows the readout of predefined data burst—in this case, 01010101. The other location is used to output the refresh trip points from the on-die thermal sensor.
What is the operating voltage?
DDR3 operates at Vdd = VddQ = 1.5V ±0.075V.
What is the output driver impedance for DDR3?
The default output driver impedance for DDR3 is 34 ohms. The impedance is based on calibration to the external 240 ohm resistor, RZQ.
What is the RESET# pin used for?
RESET# is the master reset for the DRAM. It is an active LOW, asynchronous input. When the RESET# is asserted, the DRAM outputs and ODT will tri-state. The DRAM counters, registers, and data will be unknown. A RESET must be performed as part of the power-up and initialization sequence. During this sequence, the RESET# must remain LOW for a minimum of 200µs. After power-up and initialization, RESET# may be asserted at any time. Once asserted, it must stay LOW for a minimum of 100ns and a full initialization of the part must be performed afterward.
What is "write leveling"?
For improved signaling, DDR3 modules have adopted fly-by technology for the commands, addresses, control signals, and clocks. Due to signal routing, this technology has an inherent timing skew between the clock and DQ bus at the DRAM. Write leveling is a way for the system controller to de-skew the DQ strobe (DQS) to clock relationship at the DRAM. A simple feedback feature provided by the DRAM allows the controller to detect the amount of skew and adjust accordingly.
What is "ZQ Calibration"?
The ZQ calibration command can calibrate the DRAM's output drivers (Ron) and ODT values (Rtt) over process, voltage, and temperature when a dedicated 240 ohm (±1 percent) resistor is connected from the DRAM's ZQ pin to ground. In DDR3, two different calibration commands exist: ZQ calibration long (ZQCL) and ZQ calibration short (ZQCS). ZQCL is normally used during power-up initialization and reset sequences, but may be issued at any time by the controller, depending on the system environment. ZQCS is used to perform periodic calibrations to account for small voltage and temperature variations; it requires a smaller timing window to complete.
What termination values does DDR3 offer?
DDR3 supports Rtt_Nom values of 120, 60, 40, 30, and 20 ohms. Dynamic ODT (Rtt_Wr) values are 120 and 60 ohms.
Will Micron support an extended temperature range for DDR3?
Yes. Micron DDR3 parts will support a Tcase of 0°C to 95°C.