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DDR2 SDRAM FAQs

DDR2 SDRAM(9)
Can DDR2-1066 be used with two slots?
Using DDR2-1066 with two slots is unrealistic; simulations have not shown acceptable margins.
How does on-die termination (ODT) affect power consumption?
On-die termination (ODT) power is very application-dependent. ODT is also variable, depending on the setting in the EMR of the DRAM. Use the DDR2 power calculator to determine the values.

In a point-to-point system, ODT would only be active on WRITE cycles, and would not consume power during idle and READ cycles. On-board termination would consume power in these instances. ODT power should be about 2–3 percent of the total DDR2 DRAM power in a typical application.
How much power does the Vref power pin draw?
The Vref pin does not draw any power, only leakage current, which is less than 5µA.
Is VREF allowed to float during self refresh mode?
No, it must be maintained at VDDQ/2.
Should DDR2 SDRAM always have ODT turned on?
It’s not recommended, as the SDRAM reads will lose voltage margin; but technically, it is allowed.
Can the DLL be disabled in DDR2? Can DDR2 be put into DLL Disable mode similar to DDR3?
Although in some cases the DRAM may work with the DLL off, this mode of operation is not documented nor supported by JEDEC. Therefore, each DRAM design may behave differently when configured to run with the DLL disabled. Micron does not support or guarantee operation with the DLL disabled. Running the DRAM with the DLL disabled may cause the device to malfunction and/or violate some DRAM output timing specifications.
What is the DDR2 RDQS pin for?
The sole purpose of RDQS is to support the use of a x8-based RDIMM in a x4-based RDIMM system. The RDQS pin enables a x8 DDR2 SDRAM to emulate two x4s.
What is the maximum clock rate for DDR2 when it’s used with a single-ended DQS?
The answer depends on the design implementation. Data setup and hold timing should be designed to have 150ps or more of margin.  There are Single-Ended DQS Slew Rate derating tables in the data sheet that must be used in evaluating the timing. It is recommended to fully analyze the timing in calculations, as well as using signal integrity simulations and hardware characterization.
Is it OK to run clock frequencies lower than indicated in the DDR2 data sheet?
For a READ operation, the DRAM edge-aligns the strobe(s) with the data. Most controllers sense the strobe to determine where the data window is positioned. This fine strobe/data alignment requires that each DRAM have an internal DLL. The DLL is tuned to operate for a finite frequency range, which is identified in each DRAM data sheet. Running the DRAM outside these specified limits may cause the DLL to become unpredictable. The DRAM is tested to operate within the data sheet limits. Micron does not suggest or guarantee DRAM operation outside these predefined limits.