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DRAM FAQs

DRAM(10)
DDR4 SDRAM(12)
What newer power saving features does DDR4 provide compared to DDR3?

DDR4 added several new power saving features over DDR3, including:

1. Lower power pseudo-open drain drivers for the DQ pins

2. Optional ODT Input Buffer Disable Mode For Power-Down feature

3. Optional Maximum Power Saving Mode feature

4. Optional Command Address Latency (CAL)

What new features does DDR4 have that DDR3 did not have?

DDR4 has more than 20 new features compared to DDR3, focused on power saving, performance, manufacturability and reliability. These features, coupled with DDR4’s 1.2v core, can provide power savings of 25% compared to standard DDR3. DDR4’s architecture and added performance features offer a substantial performance boost in bandwidth and command scheduling, which can be realized for 100% or better effective bandwidth increase. Premium DDR4 offers over 170% faster max data rates than top-tier DDR3, with speeds as high as 3200MT/s.

Can DDR4 operate at slower DDR3 speeds?

DDR4 is backward compatible as far back as DDR3-1333. For systems that do not need speed increases above DDR3-1333 and DDR3-1600, DDR4 can support these slower bandwidth requirements with substantially lower power requirements.

Where are DDR4 devices manufactured?

DDR4 is produced in Micron fabs around the world, including Virginia, Japan, and Taiwan.

Are there any features on DDR3 that have been eliminated by DDR4?

Not really; however, DDR4 does not require an external VREFDQ, but it does provide an internally generated VREFDQ that requires calibration by the DRAM controller.

Does DDR4 use the same signaling protocol as DDR3?

Not exactly.  DDR4 still uses VTT mid-point termination on the data bus for good signal quality, however it uses pseudo open-drain drivers for less switching current compared to full push-pull drivers.

Does DDR4 use the same power sources as DDR3?

No, DDR3 requires VDD and VDDQ equal to 1.5V, VREFCA equal to 0.5 x VDD, and VREFDQ equal to 0.5 x VDDQ, while DDR4 requires VDD and VDDQ equal to 1.2V, VREFCA equal to 0.5 x VDD, and VPP equal to 2.5V.

What is DDR4’s VPP supply, and why does DDR4 have it?

The VPP supply replaces the internal word-line charge pumps that were present in earlier versions of DDR SDRAM including DDR3. Providing this voltage externally allows DDR4 to operate at a lower voltage level in a more cost-effective manner rather than providing the internal charge pumps.

Are DDR3 and DDR4 pin-to-pin compatible to each other?

No, the DDR4 ballout is different from the DDR3 ballout. However, DDR4 uses the same package sizes and ball pitch as DDR3.

DDR4 doubled the data rate of DDR3—did the prefetch also double from 8n to 16n?

No, DDR4 kept the 8n-bit prefetch used by DDR3; thus, BL8 is still supported.

Did DDR4 finally add boundary-scan or JTAG support?

DDR4 now has a Connectivity test mode to simplify testing with a boundary scan enabled controller. Designed to work with a boundary scan device, CT mode is supported in all Micron ×4, ×8, and ×16 devices (Though JEDEC requires only for x16). CT model allows a boundary scan device to load and read a pattern from a DDR4 in CT mode. DDR4 does not directly support IEEE 1149.1.

Does DDR4 support DLL Disable Mode or DLL-off Mode for slower clock rates?

Yes, DDR4 supports DLL-off Mode similar to DLL Disable Mode in DDR3, up to 125 MHz

DDR3 SDRAM(15)
Are the DDR3 voltages backward compatible?

Yes, all of our 1.35V parts are backward compatible with 1.5V.

Can I run Micron’s DDR3 memory at clock speeds slower than 300 MHz?
Yes. Micron supports the optional feature to disable the DLL using the Mode Register, called DLL Disable Mode. This feature allows the DRAM to operate at frequencies slower than 125 MHz, however the timing still must satisfy the refresh interval. When operating in DLL Disable Mode, special conditions apply - refer to the device data sheets for details and restrictions.
How do I determine my CAS WRITE latency (CWL)?
In DDR3, only one CWL is valid for a given clock frequency range. - tCKavg = 2.5ns to <3.3ns, CWL = 5 - tCKavg = 1.875ns to <2.5ns, CWL = 6 - tCKavg = 1.5ns to <1.875ns, CWL = 7 - tCKavg = 1.25ns to <1.5ns, CWL = 8
What component densities are available?
Micron supports 1Gb, 2Gb, 4Gb, and 8Gb densities.
What is burst chop?
Due to use of the 8n-prefetch architecture in DDR3, a true burst length of 4 (BL4) was not possible. Burst chop mode became available in DDR3 to help mitigate this, and is also available in newer SDRAMs. Using Burst Chop in DDR3 the last 4 bits of the burst are essentially masked. Timing in Burst Chop 4 (BC4) cannot be treated like a true BL4. For READ-to-WRITE, select WRITE-to-READ, and select WRITE-to-PRECHARGE transitions, the system can achieve clock savings in the BC4 mode. While doing READ-to-READ or WRITE-to-WRITE transitions, timing must be treated like BL8; no clock savings will be realized.  DDR3 supports only either BC4 or BL8, although there is also an on-the-fly (OTF) option to switch between them via address pin A12.  Refer to the device data sheets for more details.
What is Dynamic ODT?
Dynamic ODT (Rtt_WR) enables the DRAM to change termination values during a WRITE without having to perform a MODE REGISTER SET command. When Rtt_Wr and Rtt_Nom are both enabled, the DRAM will change termination values from Rtt_Nom to Rtt_Wr at the beginning of the WRITE burst. Once the burst is complete, the termination will be changed back to the Rtt_Nom value. Rtt_Wr can be used independently of Rtt_Nom, but termination will be on WRITEs only.
What is the difference between the ZQCL and ZQCS commands?
ZQCL stands for ZQ calibration long. This command must be issued during the power-up and initialization sequence and requires 512 clocks to complete. After power-up and initialization, the command can be issued any time the DRAM is idle. These subsequent commands only require 246 clocks. This command is used when there is more impedance error correction required than a ZQCS can provide. ZQCS stands for ZQ calibration short. This command can be performed any time the DRAM is idle. One ZQCS can correct a minimum of 0.5 percent impedance error and requires 64 clocks.
What is the "MPR"?
MPR is a multi-purpose register. It is a specialized register designed to allow predefined data to be read out of the DRAM. Data is one bit wide and is output on a prime DQ. For Micron DDR3 parts, the prime DQs are DQ0 for x4/x8 and DQ0/DQ8 for x16. Two locations in the MPR are defined. One allows the readout of predefined data burst—in this case, 01010101. The other location is used to output the refresh trip points from the on-die thermal sensor.
What is the operating voltage?
DDR3 operates at Vdd = VddQ = 1.5V ±0.075V. DDR3L operates at Vdd = VddQ = 1.35V (1.283–1.45V) 
What is the output driver impedance for DDR3?
The default output driver impedance for DDR3 is 34 ohms. The impedance is based on calibration to the external 240 ohm resistor, RZQ.
What is the RESET# pin used for?
RESET# is the master reset for the DRAM. It is an active LOW, asynchronous input. When the RESET# is asserted, the DRAM outputs are disabled and ODT will turn off (High-Z). The DRAM counters, registers, and data will be unknown. A RESET must be performed as part of the power-up and initialization sequence. During this sequence, the RESET# must remain LOW for a minimum of 200µs. After power-up and initialization, RESET# may be asserted at any time. Once asserted, it must stay LOW for a minimum of 100ns and a full initialization of the part must be performed afterward.
What is "write leveling"?
For improved signaling, DDR3 modules have adopted fly-by technology for the commands, addresses, control signals, and clocks. Due to signal routing, this technology has an inherent timing skew between the clock and DQ bus at the DRAM. Write leveling is a way for the system controller to de-skew the DQ strobe (DQS) to clock relationship at the DRAM. A simple feedback feature provided by the DRAM allows the controller to detect the amount of skew and adjust accordingly.
What is "ZQ Calibration"?
The ZQ calibration command can calibrate the DRAM's output drivers (Ron) and ODT values (Rtt) over process, voltage, and temperature when a dedicated 240 ohm (±1 percent) resistor is connected from the DRAM's ZQ pin to ground. In DDR3, two different calibration commands exist: ZQ calibration long (ZQCL) and ZQ calibration short (ZQCS). ZQCL is normally used during power-up initialization and reset sequences, but may be issued at any time by the controller, depending on the system environment. ZQCS is used to perform periodic calibrations to account for small voltage and temperature variations; it requires a smaller timing window to complete.
What termination values does DDR3 offer?
DDR3 supports RTT_nom values of 120, 60, 40, 30, and 20 ohms. Dynamic ODT values (RTT_WR) are 120 and 60 ohms.
Will Micron support an extended temperature range for DDR3?
Yes. Micron DDR3 parts will support a Tcase of 0°C to 95°C.
DDR2 SDRAM(9)
Can DDR2-1066 be used with two slots?
Using DDR2-1066 with two slots is unrealistic; simulations have not shown acceptable margins.
How does on-die termination (ODT) affect power consumption?
On-die termination (ODT) power is very application-dependent. ODT is also variable, depending on the setting in the EMR of the DRAM. Use the DDR2 power calculator to determine the values.

In a point-to-point system, ODT would only be active on WRITE cycles, and would not consume power during idle and READ cycles. On-board termination would consume power in these instances. ODT power should be about 2–3 percent of the total DDR2 DRAM power in a typical application.
How much power does the Vref power pin draw?
The Vref pin does not draw any power, only leakage current, which is less than 5µA.
Is VREF allowed to float during self refresh mode?
No, it must be maintained at VDDQ/2.
Should DDR2 SDRAM always have ODT turned on?
It’s not recommended, as the SDRAM reads will lose voltage margin; but technically, it is allowed.
Can the DLL be disabled in DDR2? Can DDR2 be put into DLL Disable mode similar to DDR3?
Although in some cases the DRAM may work with the DLL off, this mode of operation is not documented nor supported by JEDEC. Therefore, each DRAM design may behave differently when configured to run with the DLL disabled. Micron does not support or guarantee operation with the DLL disabled. Running the DRAM with the DLL disabled may cause the device to malfunction and/or violate some DRAM output timing specifications.
What is the DDR2 RDQS pin for?
The sole purpose of RDQS is to support the use of a x8-based RDIMM in a x4-based RDIMM system. The RDQS pin enables a x8 DDR2 SDRAM to emulate two x4s.
What is the maximum clock rate for DDR2 when it’s used with a single-ended DQS?
The answer depends on the design implementation. Data setup and hold timing should be designed to have 150ps or more of margin.  There are Single-Ended DQS Slew Rate derating tables in the data sheet that must be used in evaluating the timing. It is recommended to fully analyze the timing in calculations, as well as using signal integrity simulations and hardware characterization.
Is it OK to run clock frequencies lower than indicated in the DDR2 data sheet?
For a READ operation, the DRAM edge-aligns the strobe(s) with the data. Most controllers sense the strobe to determine where the data window is positioned. This fine strobe/data alignment requires that each DRAM have an internal DLL. The DLL is tuned to operate for a finite frequency range, which is identified in each DRAM data sheet. Running the DRAM outside these specified limits may cause the DLL to become unpredictable. The DRAM is tested to operate within the data sheet limits. Micron does not suggest or guarantee DRAM operation outside these predefined limits.
SDRAM(3)
Can CKE be tied HIGH throughout SDRAM operation (initialization and normal operation)?
JEDEC does not specify the exact state of CKE during initialization; it is supplier specific. Micron strongly recommends CKE be kept at an LVTTL logic LOW before applying a stable CLK signal. During normal operation, CKE can be tied HIGH. The initial LOW state of CKE prevents parts from receiving an illegal LMR command, which could put the part into an unknown or unexpected state.
Can the SDRAM clock frequency be changed?
Micron SDR SDRAM data sheets require that the clock frequency be constant during access or precharge states. However, because there is no DLL in SDRAM, it may be possible to shift the clock frequency dynamically, though this is not recommended by Micron. If a design requires shifting frequency, lowering SDRAM frequency may be OK, even if you are not doing an LMR and CAS latency change. In case of increasing frequency, ensure tCK and CAS latency specifications are met. In either case, all other data sheet timing specifications must always be adhered to.
Is there a minimum clock frequency for SDR SDRAM?

Because SDR SDRAM does not have a DLL, there is no minimum clock frequency.  However, if the device is clocked at lower frequencies, it is still important to maintain a reasonably fast slew rate on the clock edges to avoid risk of setup and/or hold-time violations. Also, for operating frequencies of 45 MHz, tCKS = 3.0ns. For more information, see LVTTL Derating for SDRAM Slew Rate Violations (TN-48-09).

DDR SDRAM(10)
Can a -6 or -6T speed grade DDR part be substituted with a faster -5B speed grade part without encountering problems due to the 2.6V operation? Can the customer run the part at slower speeds?
Yes, all speed grades are backward-compatible. So, -5B can run at -6T timing and -6T voltage levels (2.5V). At DDR400 speeds, Micron parts require (in compliance with JEDEC standard) Vdd = VddQ = 2.6V ±0.1V. At slower speed grades (DDR333 through DDR200), the Micron parts are backward compatible, only requiring Vdd = VddQ = 2.5V ±0.2V.
Do I need a separate voltage regulator to supply Vref power?
There is no requirement to use a separate regulator to supply Vref for Micron's DDR SDRAM. However, because Vref is the reference voltage for all single-ended inputs, any noise due to sharing the regulator with other I.C.s on a board or by using a voltage divider from the VDD supply, will directly impact the noise margin on those inputs. Many multi-drop systems already have a designated voltage regulator for DDR memory. Other systems that incorporate point-to-point memory typically use a simple voltage divider resistor network between VDD and VSS.  System designers should evaluate the priorities and trade-offs for each particular system and use the power supply scheme that is optimal for the system. 
How long does Micron plan to support 3.3V SDRAM?
Micron is supporting and plans to support SDR for several years. Contact your local Micron sales representative for more information.
How long does Micron plan to support DDR?
Micron is supporting and plans to support DDR for several years. Contact your local Micron sales representative for more information.
Is VREF required during self refresh? I would like to put DDR memory in self refresh mode and turn off power to the CPU (the system is battery-operated). Can I disable VREF and still have correct self refresh operation?
Yes. VREF is required during self refresh. All DDR components' on-chip address counters are still operational during self refresh mode, so VDD must be maintained within the stated data sheet limits. Again, VREF must not be disabled after the DDR memory is put into self refresh mode. Doing so could easily result in inadvertently exiting self refresh. You should understand that VREF draws almost no power; any current drawn by VREF is negligible when compared to VTT and the core VDD. DDR components typically use a differential pair common source amplifier as their SSTL_2 input receiver. Because the VREF pin is used primarily as an input to this circuit, its current draw is low. It is so low, in fact, that the device’s input leakage current (~5µA) can be considered the maximum current requirement for the VREF pin. Typical VTT power is drawn from other places on the board and depends on the other components used on the module/system in addition to DRAM devices.
On DDR, what happens when DQS write postamble (tWPST) maximum specification is exceeded? What problems could this cause?
The tWPST maximum specification is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly.
On DRAM, can a READ or WRITE command be given instead of a refresh?
If all of the different row addresses are read or written within the refresh time (tREF), a refresh need not be performed. (The different row addresses are the same number of rows as the number of REFRESH cycles. For example, in the case of 8,192/64ms, the number of rows equal 8,192.) With DRAM, selecting row addresses causes the same action as a refresh, so a REFRESH command need not be executed.
On DRAM, can unused DQ (data) pins be left floating?
Micron recommends that unused data pins be tied HIGH or LOW. Because Micron uses CMOS technology in DRAM manufacturing, letting them float could leave the pins susceptible to noise and create a random internal input level. Unused pins can be connected to VDD or ground through resistors.
What is the difference between no connect (NC), no function (NF), and do not use (DNU) pins? How should external connections to them be handled?
An NC (no connect) pin indicates a device pin to which no internal connection is present or allowed. Micron recommends that no external connection be made to this pin. However, if a connection is inadvertently made, it will not affect device operation. Sometimes NC pins could be reserved for future use. Refer to the part’s data sheet to confirm whether the pin is reserved for future use. An NF (no function) pin indicates a device pin that is electrically connected to the device but for which the signal has no function in the device operation. Micron strongly recommends that no external connection be made to this pin. A DNU (do not use) pin indicates a device pin to which there may or may not be an internal connection but to which no external connections are allowed. Micron requires that no external connection be made to this pin. Refer to the part’s data sheet for more details.
What is the maximum junction temperature at which DDR SDRAM functionality is guaranteed?
Please refer to page 3 of Micron’s technical note on thermal applications: TN-00-08. If functionality or operation is not a concern, refer to storage temperature specification limits on the part’s data sheet.
GDDR5(3)
How does Graphics DRAM differ from regular DRAM?
Graphics DRAM is a category of DDR SDRAM designed to handle very large bandwidth requirements. Unlike standard DRAM, graphics DRAM is typically soldered down on the same PCB as the SoC and always supports 32 DQs per memory component. Besides graphics cards and game consoles, graphics DRAM is being used in high-bandwidth applications like networking, automotive and high-performance computing.
What features and functions does GDDR5 have versus previous generations of Graphics DRAM?
GDDR5 provides higher densities, lower external voltage and more than twice the memory bandwidth compared to its predecessor, GDDR3. GDDR5’s 4X relationship between data rate and the CK clock is unique compared to the 2X relationship in DDR3 and GDDR3.
Is GDDR5 a direct replacement for GDDR3?
No, GDDR5 is not a direct replacement for GDDR3 due to package size differences. GDDR3 has a 136-ball BGA package while GDDR5 has a 170-ball BGA package.
GDDR5X(7)
How does Graphics DRAM differ from regular DRAM?
Graphics DRAM is a category of DDR SDRAM designed to handle very large bandwidth requirements. Unlike standard DRAM, graphics DRAM is typically soldered down on the same PCB as the SoC and always supports 32 DQs per memory component. Besides graphics cards and game consoles, graphics DRAM is being used in high-bandwidth applications like networking, automotive and high-performance computing.
What features and functions does GDDR5X have compared to previous generations of Graphics DRAM?
GDDR5X provides higher densities and lower external voltage (1.35V) compared to its predecessor, GDDR5. GDDR5X also doubles the bandwidth (10–16 Gb/s) of GDDR5 while remaining on traditional discrete package technology (FBGA).
Can GDDR5X operate in GDDR5-like mode?

Yes, GDDR5X has two operation modes:

  • QDR mode: Supports speeds of 10 Gb/s and above
  • DDR mode: Supports 0.2–6 Gb/s speeds and is compatible with GDDR5
Does GDDR5X support JTAG boundary scan?
Yes, GDDR5X has IEEE 1149.1 compliant boundary scan.
What is Micron’s competitive position with GDDR5X?
Micron is the first memory supplier in the industry supporting GDDR5X in mass production.
Is GDDR5X a JEDEC standard?
Yes, the GDDR5X SGRAM standard was first published in Dec. 2015 as JESD232. The latest JEDEC release is JESD232A.
Does GDDR5X replace GDDR5?
GDDR5X is not a direct replacement for GDDR5 due to package size differences. GDDR5 has a 170-ball, 0.8mm-pitch BGA package while GDDR5X has a 190-ball, 0.65mm-pitch package.
GDDR6(8)
How does graphics DRAM differ from regular DRAM?
Graphics DRAM is a category of DDR SDRAM designed to handle very large bandwidth requirements. Unlike standard DRAM, graphics DRAM is typically soldered down on the same PCB as the SoC and always supports 32 DQs per memory component. Besides graphics cards and game consoles, graphics DRAM is being used in high-bandwidth applications like networking, automotive and high-performance computing.
What features and functions does GDDR6 have compared to previous generations of graphics DRAM?

GDDR6 provides higher densities than previous-generation graphics memory. It doubles the bandwidth of GDDR5, extending past GDDR5X speeds. In addition, it is based on a dual-channel architecture, which enables a huge performance increase while still providing backward compatibility to GDDR5 memory access size.

Can GDDR6 operate in GDDR5-like mode?
No
Can GDDR6 operate in GDDR5X-like mode?
Yes
Does GDDR6 support JTAG boundary scan?
Yes, GDDR6 has IEEE 1149.1 compliant boundary scan
What is Micron’s competitive position with GDDR6?
Micron is leveraging its GDDR5X-based high-speed signaling know-how from more than two years of design, mass production, test and application learning in Micron GDDR6 products. This allows Micron to remain in the leading position on high-speed signaling with traditional memory components.
Is GDDR6 a JEDEC standard?
Yes, the GDDR6 SGRAM standard was first published in July 2017 as JESD250.
Does GDDR6 replace GDDR5 or GDDR5X?
GDDR6 is not a direct replacement for GDDR5 nor GDDR5X due to package size differences. GDDR5 has a 170-ball, 0.8mm-pitch BGA package, GDDR5X has a 190-ball, 0.65-mm pitch BGA package and GDDR6 has a 180-ball, 0.75mm-pitch BGA package.
RLDRAM(6)
Are CK/CK# and DK/DK# true differential inputs?
Yes, the CK/CK# and DK/DK# input buffers are true differential inputs. Both sets of clocks need to meet the specifications that are defined in the Clock Input Operating Conditions tables in the RLDRAM data sheets.
Can I connect the “Do Not Use” (DNU) pins to ground (GND)?
Yes. However, when on-die termination (ODT) is enabled, the DNU pins will be connected to VTT. Connecting the DNU pins to GND under these circumstances will cause a substantially larger load on your VTT supply.
How is RLDRAM II memory similar to SRAM?
 Simplified command set of only four commands and a Fast cycle time, as low as 7ns tRC
I’ve heard about the new multibank write feature on RLDRAM 3. What exactly is this feature?
Multibank write is a feature that allows for SRAM-like random read access time. Using this feature can reduce RLDRAM 3’s already low tRC (<10ns) by up to 75% during reads. Through the RLDRAM 3 mode register, you can choose to write to one, two, or four banks simultaneously. By storing identical data in multiple banks, the memory controller has the flexibility to determine which bank to read the data from in order to minimize tRC delay.
What new features does RLDRAM 3 add?
 Multibank write that enables SRAM-like random read capabilities. MULTIBANK REFRESH makes managing refresh overhead more flexible than ever, allowing refresh of one to four banks simultaneously. RLDRAM3 also supports a mirror function to ease layout of clamshell designs.
Will I be able to leverage any existing DRAM technology to ease the adoption of RLDRAM 3 in my system?
Yes. Even though RLDRAM 3 is a new architecture, it leverages many features from both DDR3 and RLDRAM 2 to make adoption and integration as easy as possible. The command protocol, addressing, and strobing scheme are the same as RLDRAM 2, while the I/O, AC timing, and read training register very closely resemble those found in DDR3.
LPDRAM(11)
Are Micron's LPDRAM products green/RoHS compliant?
Yes. Micron’s green engineering program is RoHS-compliant and conforms with most of the world’s emerging environmental standards, including those in Asia and Europe.
Are your LPDRAM parts JEDEC-compliant?
We design our parts to meet or exceed the JEDEC specification. As standards change, we will make the necessary changes to ensure our parts meet new specifications. Any changes made will be noted in a product change notice (PCN) and sent to our customers.
Does Micron's LPDRAM cost more than standard DRAM?
It depends. Density plays a major role in price comparisons between LPDRAM and standard SDR/DDR. Also, since LPDRAM is offered in standard configurations of x16, x32 and x64, you may be able to reduce your overall BOM cost if your application currently uses two x16 components to support a x32 bus. You could use one x32 LPDRAM instead of two x16 standard DRAM. Contact your local rep for cost information.
How does LPDDR3 differ from DDR3L-RS?

LPDDR3 is optimized for battery life and portability. DDR3L-RS is a low IDD6 version of the DDR3L die and offers a balance in price versus performance, along with improved standby power.

How does LPDDR3 differ from LPDDR2?

LPDDR3 increases performance to 1600 Mb/s (versus 1066 Mb/s for LPDDR2). Additional changes include write leveling, C/A (command/address) training, and a lower I/O capacitance limit to improve timing.

How does LPDDR4 differ from LPDDR3?

LPDDR4 increases data rate to 3200Mbps ~ 4266Mbps/pin, using LVSTL(Low Voltage Swing Terminated Logic).  Die organization has changed from x32 1ch (LPDDR3) to x16/x8 2ch, and added x16/x8 1ch. There are other new features on LPDDR4 for higher speed, lower power consumption.

The part I was using is obsolete and the replacement is a faster speed grade. Can I run the LPDRAM parts at a lower speed?
Yes. A LPDRAM part can be run at any speed equal to or slower than its rated speed grade.
What is LPDRAM?
Optimized for products where power consumption is a concern, our low-power LPDRAM devices combine leading-edge technologies and packaging options to meet space requirements and extend battery life. LPDRAM is available with DDR/SDR interface.
What is the life expectancy of Micron's LPDRAM products?
We're excited about this fast-growing market. We plan to manufacture LPDRAM for many years to come and plan to continue to shrink our designs to achieve higher densities.
What makes Micron's LPDRAM unique?
We offer a comprehensive LPDRAM product portfolio, with a wide range of densities and package options (including JEDEC-standard VFBGA, Known Good Die, and package-on-package). With nearly a decade of LPDRAM experience, our worldwide technical support team can provide the expertise and assistance you need to get your designs to market faster.
What’s the difference between Mobile DRAM and LPDRAM?
There is no difference; Mobile DRAM and LPDRAM are the same product. We opted to add the "LP" prefix to our Mobile DRAM product line to align with the common terminology used throughout the industry and to ensure our customers know at a glance that our Mobile DRAM is a low-power memory device. In addition to the family name change, Mobile DDR SDRAM and Mobile SDR SDRAM are now called Mobile LPDDR and Mobile LPSDR, respectively. Our Web site has been wholly converted to the LPDRAM naming convention, but because we’re updating our PDFs as they come up for review you may see a few older technical documents that still use the old Mobile DRAM terminology.