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What are some of the additional power-saving features of DDR4?

Some new power-savings features in DDR4 include pseudo open-drain DQs (for read and write I/O power reduction), data-bit inversion (DBI), and command address latency (CAL).

What is the value of DDR4?

DDR4 has more than 20 new features compared to DDR3, focused on power saving, performance, manufacturability and reliability. These features, coupled with DDR4’s 1.2v core, can provide power savings of 25% compared to standard DDR3. DDR4’s architecture and added performance features offer a substantial performance boost in bandwidth and command scheduling, which can be realized for 100% or better effective bandwidth increase. Premium DDR4 offers over 170% faster max data rates than top-tier DDR3, with speeds as high as 3200MT/s.

Can DDR4 operate at slower DDR3 speeds?

DDR4 is backward compatible as far back as DDR3-1333. For systems that do not need speed increases above DDR3-1333 and DDR3-1600, DDR4 can support these slower bandwidth requirements with substantially lower power requirements.

Where will DDR4 devices be manufactured?

DDR4 will be produced in Micron fabs around the world, including Virginia, Singapore, and Taiwan.

Are there any features on DDR3 that have been eliminated by DDR4?

Not really; however, DDR4 does not require an external VREFDQ, but it does provide an internally generated VREFDQ that requires calibration by the DRAM controller.

Does DDR4 use the same signaling protocol as DDR3?

DDR4 uses the same VTT mid-point termination methodology (SSTL1.5) on the address, command, and control pins as DDR3; however, DDR4 uses VDD termination (POD12) on the data bus due to the use of pseudo open-drain I/Os for improved signal quality and less switching current.

Does DDR4 use the same power sources as DDR3?

No, DDR3 requires VDD and VDDQ equal to 1.5V, VREFCA equal to 0.5 x VDD, and VREFDQ equal to 0.5 x VDDQ, while DDR4 requires VDD and VDDQ equal to 1.2V, VREFCA equal to 0.5 x VDD, and VPP equal to 2.5V.

What is DDR4’s VPP supply, and why does DDR4 have it?

The VPP supply replaces the internal word-line charge pumps. Providing this voltage externally allows the DDR4 to operate at a lower voltage level in a more cost-effective manner rather than providing the internal charge pumps.

Are DDR3 and DDR4 pin-to-pin compatible to each other?

No, the DDR4 ballout is different from the DDR3 ballout. However, DDR4 uses the same package sizes and ball pitch as DDR3.

DDR4 doubled the data rate of DDR3—did the prefetch also double from 8n to 16n?

No, DDR4 kept the 8-bit prefetch used by DDR3; thus, BL8 is still supported.

Did DDR4 finally add boundary-scan or JTAG support?

For x16 devices, yes; DDR4 added a “connectivity test” mode that allows electrical verification of balls after connection to a memory interface.

Are there any new inputs/outputs required to support DDR4?

Yes, seven new inputs/outputs were added: VPP, BG (bank group), DBI_n, ACT_n, PAR, Alert_n, and TEN. However, the ball count increased by only three (73 to 76 balls).

Does DDR4 support DLL off mode for very slow clock rates?

Yes, DDR4 supports DLL-off mode similar to DDR3, up to 125 MHz.

Are the DDR3 voltages backward compatible?

Yes, all of our 1.35V parts are backward compatible with 1.5V.

Can I run Micron’s DDR3 memory at clock speeds slower than 300 MHz?
Yes. Micron supports the optional feature to disable the DLL. This feature allows the DRAM to operate at frequencies slower than 125 MHz. A minimum clock rate is not specified, but the timing still must satisfy the refresh interval (tREFI). When operating in DLL disable mode, special conditions apply: - no support of on-die termination (ODT); ODT must be disabled or turned off - both CL and CWL must be equal to 6 - data out is no longer edge-aligned to the clock and read latency will be AL + CL - 1 tCK
How do I determine my CAS WRITE latency (CWL)?
In DDR3, only one CWL is valid for a given clock frequency range. - tCKavg = 2.5ns to <3.3ns, CWL = 5 - tCKavg = 1.875ns to <2.5ns, CWL = 6 - tCKavg = 1.5ns to <1.875ns, CWL = 7 - tCKavg = 1.25ns to <1.5ns, CWL = 8
How do I determine the amount of time between ZQCS commands?
Each ZQCS command can correct a minimum of 0.5 percent impedance error within 64 clocks. To calculate the ZQCS interval, use the following formula: ZQCS Interval =ZQCorrection (Tsens x Tdriftrate) + (VSens x Vdriftrate) For the sensitivities, use the MAX number from the ODT voltage and temperature sensitivity table in the component specification. Drift rates will vary from system to system. ZQCorrection equals 0.5%/64 clocks.
What component densities are available?
JEDEC has defined DDR3 densities of 512Mb–8Gb; Micron plans to support 1Gb through 4Gb.
What is burst chop?
Due to DDR3's use of the 8n-prefetch architecture, a true burst of 4 is not possible with most designs. Burst chop mode (BC4) is unique to DDR3. In this mode, the last 4 bits of the burst are essentially masked. Timing in BC4 cannot be treated like a true BL4. For READ-to-WRITE, select WRITE-to-READ, and select WRITE-to-PRECHARGE transitions, the system can achieve clock savings in the BC4 mode. While doing READ-to-READ or WRITE-to-WRITE transitions, timing must be treated like BL8; no clock savings will be realized.
What is Dynamic ODT?
Dynamic ODT (Rtt_WR) enables the DRAM to change termination values during a WRITE without having to perform a MODE REGISTER SET command. When Rtt_Wr and Rtt_Nom are both enabled, the DRAM will change termination values from Rtt_Nom to Rtt_Wr at the beginning of the WRITE burst. Once the burst is complete, the termination will be changed back to the Rtt_Nom value. Rtt_Wr can be used independently of Rtt_Nom, but termination will be on WRITEs only.
What is the difference between the ZQCL and ZQCS commands?
ZQCL stands for ZQ calibration long. This command must be issued during the power-up and initialization sequence and requires 512 clocks to complete. After power-up and initialization, the command can be issued any time the DRAM is idle. These subsequent commands only require 246 clocks. This command is used when there is more impedance error correction required than a ZQCS can provide. ZQCS stands for ZQ calibration short. This command can be performed any time the DRAM is idle. One ZQCS can correct a minimum of 0.5 percent impedance error and requires 64 clocks.
What is the "MPR"?
MPR is a multi-purpose register. It is a specialized register designed to allow predefined data to be read out of the DRAM. Data is one bit wide and is output on a prime DQ. For Micron DDR3 parts, the prime DQs are DQ0 for x4/x8 and DQ0/DQ8 for x16. Two locations in the MPR are defined. One allows the readout of predefined data burst—in this case, 01010101. The other location is used to output the refresh trip points from the on-die thermal sensor.
What is the operating voltage?
DDR3 operates at Vdd = VddQ = 1.5V ±0.075V.
What is the output driver impedance for DDR3?
The default output driver impedance for DDR3 is 34 ohms. The impedance is based on calibration to the external 240 ohm resistor, RZQ.
What is the RESET# pin used for?
RESET# is the master reset for the DRAM. It is an active LOW, asynchronous input. When the RESET# is asserted, the DRAM outputs and ODT will tri-state. The DRAM counters, registers, and data will be unknown. A RESET must be performed as part of the power-up and initialization sequence. During this sequence, the RESET# must remain LOW for a minimum of 200µs. After power-up and initialization, RESET# may be asserted at any time. Once asserted, it must stay LOW for a minimum of 100ns and a full initialization of the part must be performed afterward.
What is "write leveling"?
For improved signaling, DDR3 modules have adopted fly-by technology for the commands, addresses, control signals, and clocks. Due to signal routing, this technology has an inherent timing skew between the clock and DQ bus at the DRAM. Write leveling is a way for the system controller to de-skew the DQ strobe (DQS) to clock relationship at the DRAM. A simple feedback feature provided by the DRAM allows the controller to detect the amount of skew and adjust accordingly.
What is "ZQ Calibration"?
The ZQ calibration command can calibrate the DRAM's output drivers (Ron) and ODT values (Rtt) over process, voltage, and temperature when a dedicated 240 ohm (±1 percent) resistor is connected from the DRAM's ZQ pin to ground. In DDR3, two different calibration commands exist: ZQ calibration long (ZQCL) and ZQ calibration short (ZQCS). ZQCL is normally used during power-up initialization and reset sequences, but may be issued at any time by the controller, depending on the system environment. ZQCS is used to perform periodic calibrations to account for small voltage and temperature variations; it requires a smaller timing window to complete.
What termination values does DDR3 offer?
DDR3 supports Rtt_Nom values of 120, 60, 40, 30, and 20 ohms. Dynamic ODT (Rtt_Wr) values are 120 and 60 ohms.
Will Micron support an extended temperature range for DDR3?
Yes. Micron DDR3 parts will support a Tcase of 0°C to 95°C.
Are there any supply voltage savings with 1.5V DDR2 SDRAM versus 1.55V DDR2 SDRAM?
Yes, the 1.5V DDR2 SDRAM uses about 15–20 percent less current than the 1.55V DDR2 SDRAM.
Are there any timing specification differences between 1.5V DDR2 SDRAM and 1.8V DDR2 SDRAM?
Are there any timing specification differences between 1.55V DDR2 SDRAM and 1.8V DDR2 SDRAM?
Yes, DLL-controlled output specs require some derating.
Can DDR2-1066 be used with two slots?
Using DDR2-1066 with two slots is unrealistic; simulations have not shown acceptable margins.
Can you explain how on-die termination (ODT) affects power consumption?
On-die termination (ODT) power is very application-dependent. ODT is also variable, depending on the setting in the EMR of the DRAM. Use the DDR2 power calculator to determine the values.

In a point-to-point system, ODT would only be active on WRITE cycles, and would not consume power during idle and READ cycles. On-board termination would consume power in these instances. ODT power should be about 2–3 percent of the total DDR2 DRAM power in a typical application.
How much power does the Vref power pin draw?
The Vref pin does not draw any power, only leakage current, which is less than 5µA.
Is DDR2-1066 a JEDEC standard?
Not yet, but it’s in process.
Is the ridge down the middle of the underside of FBGA packages conductive?
No, only designated balls are conductive.
Is VREF allowed to float during self refresh mode?
No, it must be maintained at VDDQ/2.
Should DDR2 SDRAM always have ODT turned on?
It’s not recommended, as the SDRAM reads will lose voltage margin; but technically, it is allowed.
Should the DLL be disabled?
Although in some cases the DRAM may work with the DLL off, this mode of operation is not documented nor supported by JEDEC. Therefore, each DRAM design may behave differently when configured to run with the DLL disabled. Micron does not support or guarantee operation with the DLL disabled. Running the DRAM with the DLL disabled may cause the device to malfunction and/or violate some DRAM output timing specifications.
What is the DDR2 RDQS pin for?
The sole purpose of RDQS is to support the use of a x8-based RDIMM in a x4-based RDIMM system. The RDQS pin enables a x8 DDR2 SDRAM to emulate two x4s.
What is the difference between 1.5V DDR2 SDRAM and 1.55V DDR2 SDRAM?
1.5V DDR2 SDRAM is not backward compatible to 1.8V operating systems, and the 1.55V DDR2 SDRAM is.
What is the maximum clock rate for DDR2 when it’s used with a single-ended DQS?
The answer depends mostly on design implementation. As long as the data setup and holds have 150ps or more of margin and there’s a fast slew rate, a single-ended DQS should be OK.
Will the device run at a slow clock (well under the slowest data sheet speed)?
For a READ operation, the DRAM edge-aligns the strobe(s) with the data. Most controllers sense the strobe to determine where the data window is positioned. This fine strobe/data alignment requires that each DRAM have an internal DLL. The DLL is tuned to operate for a finite frequency range, which is identified in each DRAM data sheet. Running the DRAM outside these specified limits may cause the DLL to become unpredictable. The DRAM is tested to operate within the data sheet limits. Micron does not suggest or guarantee DRAM operation outside these predefined limits.
Can CKE be tied HIGH throughout SDRAM operation (initialization and normal operation)?
JEDEC does not specify the exact state of CKE during initialization; it is supplier specific. Micron strongly recommends CKE be kept at an LVTTL logic LOW before applying a stable CLK signal. During normal operation, CKE can be tied HIGH. The initial LOW state of CKE prevents parts from receiving an illegal LMR command, which could put the part into an unknown or unexpected state.
Can the SDRAM clock frequency be changed?
Micron SDRAM data sheets require that the clock frequency be constant during access or precharge states (READ, WRITE, tWR, and PRECHARGE commands). At other times frequency should not matter much because there is no DLL in SDRAM however, we do not recommend it. Lowering SDRAM frequency is OK even if you are not doing an LMR and CAS latency change. In case of increasing frequency, ensure tCK and CAS latency specifications are met. In either case, all other data sheet timing specifications should be adhered to.
Is there a recommended lowest working frequency for SDRAM?
Because SDRAM does not have a DLL, there is no recommended lowest frequency. SDRAM parts will work at very low frequencies if all data sheet specifications are met. It is important to maintain a good slew rate, however, since a very slow slew rate will affect setup and hold-time transitions. Also, for operating frequencies of 45 MHz, tCKS = 3.0ns. For more information, see TN-48-09.
A customer uses a DDR -6T part at 333 MHz. Can he substitute a faster speed grade part (DDR400, -5B) without encountering problems due to the 2.6V operation? Can the customer run the part at -75 speeds?
Yes, all speed grades are backward-compatible. So, -5B can run at -6T timing and -6T voltage levels (2.5V). At DDR400 speeds, Micron parts require (in compliance with JEDEC standard) Vdd = VddQ = 2.6V ±0.1V. At slower speed grades (DDR333 through DDR200), the Micron parts are backward compatible, only requiring Vdd = VddQ = 2.5V ±0.2V.
Can I get samples?
Yes. Talk to your service representative.
Can you provide a brief description of the necessary circuit functionality we would need to employ to transition from EDO to SDRAM technology?
Synchronous DRAM, as its name suggests, is a synchronous device and is a little different from EDO. SDRAM are directly tied to the same system clock that drives all of the other subsystems. SDRAM uses a dual-bank architecture—an interleave technique that essentially allows one cell to be read while another is being prepared for a cell access. This "cell hopping" eliminates downtime between cell activities and provides good performance improvement. Since the SDRAM will operate at higher speeds, attention needs to be paid to signal layout, including transmission line techniques such as series-terminating resistors. A consequence of signal layout could be noise due to faster clocks, crosstalk, etc. At the very least, an SDRAM controller is necessary for transitioning from EDO to SDRAM technology.
Do I need a separate voltage regulator to supply Vref power?
How Vref is supplied depends on the system design. Many multi-drop systems (where there are several modules and a need for Vtt on the system board) already have a designated voltage regulator for DDR memory. In this case, the voltage regulator may have a dedicated tap for Vref. Other systems that incorporate point-to-point memory typically use a simple voltage divider resistor network between Vdd and Vss.
Does Micron provide VHDL models for DDR parts?
No. Micron no longer supports VHDL models. We can, however, provide a generic 8 Meg x 8 model (MT46LC8M8) that can be scaled to the desired model dimensions. It’s a good starting point for building a compatible DDR model. To obtain this file, contact your Micron representative or a Micron applications engineer. You could also contact Denali or Synopsys to obtain one of their models. Or you could use a suitable multi-language simulator (like Modelsim) that cosimulates Verilog and VHDL and then download our Verilog model.
How long does Micron plan to support 3.3V SDRAM?
Micron has an extensive customer base across all four densities (64–512Mb) of SDR and plans to support it for several years. Contact your local Micron sales representative for direction on the preferred part number to qualify.
How long does Micron plan to support DDR?
Micron has an extensive customer base across all four densities (256Mb–1Gb) of DDR and plans to support it for several years. Contact your local Micron sales representative for direction on the preferred part number to qualify.
Is VREF required during self refresh? I would like to put DDR memory in self refresh mode and turn off power to the CPU (the system is battery-operated). Can I disable VREF and still have correct self refresh operation?
Yes. VREF is required during self refresh. All DDR components' on-chip address counters are still operational during self refresh mode, so VDD must be maintained within the stated data sheet limits. Again, VREF must not be disabled after the DDR memory is put into self refresh mode. Doing so could easily result in inadvertently exiting self refresh. You should understand that VREF draws almost no power; any current drawn by VREF is negligible when compared to VTT and the core VDD. DDR components typically use a differential pair common source amplifier as their SSTL_2 input receiver. Because the VREF pin is used primarily as an input to this circuit, its current draw is low. It is so low, in fact, that the device’s input leakage current (~5µA) can be considered the maximum current requirement for the VREF pin. Typical VTT power is drawn from other places on the board and depends on the other components used on the module/system in addition to DRAM devices.
On DDR, can the allowed jitter tolerance be larger than +/-150ps if we use a clock of 120 MHz instead of 133 MHz? Can the allowed jitter tolerance be larger if the device is faster?
The part may have more tolerance or margin to jitter than 150ps at 133 MHz, but Micron still has the same specification for all speeds. Micron does not relax jitter specifications for a lower speed.
On DDR, what happens when DQS write postamble (tWPST) maximum specification is exceeded? What problems could this cause?
The tWPST maximum specification is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly.
On DRAM, can a READ or WRITE command be given instead of a refresh?
If all of the different row addresses are read or written within the refresh time (tREF), a refresh need not be performed. (The different row addresses are the same number of rows as the number of REFRESH cycles. For example, in the case of 8,192/64ms, the number of rows equal 8,192.) With DRAM, selecting row addresses causes the same action as a refresh, so a REFRESH command need not be executed.
On DRAM, can unused DQ (data) pins be left floating?
Micron recommends that unused data pins be tied HIGH or LOW. Because Micron uses CMOS technology in DRAM manufacturing, letting them float could leave the pins susceptible to noise and create a random internal input level. Unused pins can be connected to VDD or ground through resistors.
What is the difference between no connect (NC), no function (NF), and do not use (DNU) pins? How should external connections to them be handled?
An NC (no connect) pin indicates a device pin to which no internal connection is present or allowed. Micron recommends that no external connection be made to this pin. However, if a connection is inadvertently made, it will not affect device operation. Sometimes NC pins could be reserved for future use. Refer to the part’s data sheet to confirm whether the pin is reserved for future use. An NF (no function) pin indicates a device pin that is electrically connected to the device but for which the signal has no function in the device operation. Micron strongly recommends that no external connection be made to this pin. A DNU (do not use) pin indicates a device pin to which there may or may not be an internal connection but to which no external connections are allowed. Micron requires that no external connection be made to this pin. Refer to the part’s data sheet for more details.
What is the maximum junction temperature at which DDR SDRAM functionality is guaranteed?
Please refer to page 3 of Micron’s technical note on thermal applications: TN-00-08. If functionality or operation is not a concern, refer to storage temperature specification limits on the part’s data sheet.
How does Graphics DRAM differ from regular DRAM?

Graphics DRAM is a category of DDR SDRAM chips made to specifically handle the enormous demands of graphics processing. Unlike standard DRAM, graphics DRAM is a fixed and dedicated memory, generally combined with the graphics processing unit (GPU) – either on the graphics card or on the system board (for systems with onboard graphics). Graphics DRAM also helps shift the display and graphics-related load away from the computer’s main memory, as well as improve the performance of the GPU and the system’s display.

What features and functions does GDDR5 have versus previous generations of Graphics DRAM?
  • GDDR5 provides more than twice the memory bandwidth compared to its predecessor, GDDR3.
  • Higher densities
  • Lower external voltage
  • The specialty of GDDR5 is the 4X relationship between data rate and the CK clock, compared to the 2X relationship in DDR3 and GDDR3.
Does GDDR5 replace GDDR3?

GDDR5 is not a direct replacement to GDDR3 due to package size differences:

  • GDDR3: BGA-136
  • GDDR5: BGA-170
How does Graphics DRAM differ from regular DRAM?

Graphics DRAM is a category of DDR SDRAM chips made to specifically handle the enormous demands of graphics processing. Unlike standard DRAM, graphics DRAM is a fixed and dedicated memory, generally combined with the graphics processing unit (GPU) – either on the graphics card or on the system board (for systems with onboard graphics). Graphics DRAM also helps shift the display and graphics-related load away from the computer’s main memory, as well as improve the performance of the GPU and the system’s display.

What features and functions does GDDR5X have versus previous generations of Graphics DRAM?
  • GDDR5X provides twice the memory bandwidth compared to its predecessor, GDDR5;supported data rates are 10–16 Gb/s
  • Lower external voltage (1.35V)
  • The specialty of GDDR5X is doubling the bandwidth while remaining on traditional discrete package technologies (FBGA). This GDDR5X extends the lifespan of the graphic card ecosystem:
    • Cost-efficient assembly on conventional equipment
    • Mature assembly process guarantees high product reliability and fastest time to market
    • Similar BOM structure to GDDR5
    • Follows successful path of PCB assembly while enabling system data rates up to 1 TB/s
  • Higher densities
Can GDDR5X operate in GDDR5-like mode?

Yes, GDDR5X has two operation modes:

  • QDR mode, supporting speeds of 10 Gb/s and above
  • DDR mode, compatible with GDDR5 and supporting 0.2–6 Gb/s
Did GDDR5X finally add boundary scan or JTAG support?

Yes, GDDR5X added a connectivity test mode that allows electrical verification of balls after connection to a memory interface.

What is Micron’s competitive position with GDDR5X?

Micron is the first memory supplier in the industry ramping GDDR5X product. This puts Micron in the leading position on high-speed signaling with traditional memory components.

Is GDDR5X a JEDEC standard?

Yes, the GDDR5X standard was published in Dec 2015 as JESD232.

Does GDDR5X replace GDDR5?

GDDR5X is not a direct replacement for GDDR5 due to package size differences:

  • GDDR5X: BGA-190
  • GDDR5: BGA-170
Are CK/CK# and DK/DK# true differential inputs?
Yes, the CK/CK# and DK/DK# input buffers are true differential inputs. Both sets of clocks need to meet the specifications that are defined in the Clock Input Operating Conditions tables in the RLDRAM II memory data sheets.
Are there any new features in RLDRAM 3 not found in earlier generations of the RLDRAM product line?
Yes. Multibank write is a new feature that enables SRAM-like random read capabilities. Managing refresh overhead is now more flexible than ever with the addition of the MULTIBANK REFRESH command. With this command, you can refresh one to four banks simultaneously. We’ve also added a mirror function ball to ease layout of clamshell designs. Depending upon the state of the mirror function ball, the command and address functions are swapped across the y-axis to allow for direct connections through the PCB.
Can 2.5V or 3.3V be directly input to joint test action group (JTAG) pins?
No. The highest operating voltage that can be input to the JTAG pins is VDD + 0.3V as outlined in the TAP DC Electrical Characteristics and Operating Conditions tables in the RLDRAM II data sheets.
Can I connect the “Do Not Use” (DNU) pins to ground (GND)?
Yes. However, when on-die termination (ODT) is enabled, the DNU pins will be connected to VTT. Connecting the DNU pins to GND under these circumstances will cause a substantially larger load on your VTT supply.
Can I reload the mode register after I have been operating with READs and WRITEs on RLDRAM II memory?
Yes, the mode register can be reloaded at any time as long as all timing specifications are met. Burst length must be considered, however. If the burst length is changed, previously written data will be corrupted.
Can RLDRAM II run slower than 175 MHz?
Yes, but the DLL must be turned off. With the DLL turned off, the output data alignment with the CK will shift by about 3–4ns, which works like the outputs of RLDRAM I memory.
Does the 576Mb RLDRAM II device still support 1.8V VDDQ? Is it possible to run at 533 MHz with VDDQ = 1.8V?
It should not be a problem to run at 533 MHz with VDDQ = 1.8V. Micron has run graphics devices at 800 MHz clock at 1.8V.
Does the RLDRAM internally compensate for voltage and temperature changes when bit A8 is not selected HIGH on the RLDRAM II during setting of the mode register?
Yes. When bit A8 of the mode register is HIGH, the user places an external precision resistor between ZQ and VSS to select an output impedance. When bit A8 is LOW, the output impedance is set to 50 ohms (±30 percent). In both cases, however, the RLDRAM device periodically calibrates this impedance to compensate for shifts in voltage and temperature. This calibration is internal to the RLDRAM and does not affect the operation of the RLDRAM.
During initialization, are 2,048 clock cycles really needed between each AUTO REFRESH command?
No. Although it is still outlined in some older data sheet revisions, it is not necessary. During initialization, it is necessary for all eight banks to receive an AUTO REFRESH command tMRSC after the last valid MRS command has been issued. If you sequentially issue AUTO REFRESH commands instead of waiting 2,048 clock cycles between each command, you must perform at least 1,024 NOP commands between the last AUTO REFRESH command and the first valid command in normal operation. Either method will satisfy the requirements of the RLDRAM.
During power-up, I bring VDDQ HIGH before VDD. Will this cause a problem?
The RLDRAM II will not be adversely affected if you bring VDDQ HIGH before VDD. However, you must be aware that when you perform the sequence in this way, the DQs, DM, and all other pins with an output driver will go HIGH instead of tri-stating. These pins will remain HIGH until VDD is at the same level as VDDQ. Care should be taken to avoid bus conflicts during this period.
How can I reset the RLDRAM II device?
RLDRAM II memory can be reset using the MODE REGISTER command. Three MRS commands must be issued on consecutive clock cycles to reset the device properly. If any commands (including NOP commands) are issued between the MRS commands, the device will not be reset.
How is RLDRAM II memory similar to SRAM?
RLDRAM II memory is similar to SRAM in a variety of ways: - Simplified command set: only four commands (READ, WRITE, REFRESH, and MODE REGISTER SELECTION) - Row/columns not apparent: can clock in the full address in one clock cycle (or can be multiplexed like a standard DRAM) - Fast cycle time: 20ns tRC for the 288Mb device and as low as to 15ns tRC for the 576Mb device
I’m seeing substantial jitter on my outputs; what can I do to remedy this?
A number of things can cause jitter on RLDRAM II memory outputs. Read through the questions below to help identify the cause of the jitter. - Is the same amount of jitter seen at the DQs, QKs, and QVLD signal? If so, the jitter may be due to the DLL. The DQs, QKs, and QVLD all use the DLL to clock out their data. Micron can assist with additional debugging to determine whether any parameters are being violated that would cause the DLL to operate improperly.
- Is there jitter on the input clocks? Any jitter on CK/CK# will be transferred to the outputs.
- Does the amount of jitter change substantially with different output data? If it does, phenomena such as ISI, SSO, or crosstalk could be causing the jitter.
- Is the system properly terminated? Because proper termination is dependent on system parameters, simulation is the best way to determine termination requirements. Micron offers several tools and technical notes to assist with termination requirements:
1.“TN-49-02: Exploring the RLDRAM II Feature Set” includes descriptions and examples of data-eyes when using the on-die termination and impedance-matching features.
2. Technical notes TN-46-14 and TN-46-06 do not specifically mention RLDRAM II memory, but they have useful information about termination and techniques to ensure good signal integrity.
3. The RLDRAM Memory Part Catalog contains configuration information for IBIS and HSpice models.
I’m using RLDRAM memory. Is it possible to tie VDD and VDDQ to the same supply?
Yes. You can tie VDD and VDDQ to the same supply.
Is MAX power specified in the data sheet?
Yes, MAX power is specified in the data sheet. Because MAX power is entirely dependent on how the devices are used in a system, the power must be calculated based on information found in the data sheet. In addition to the information found in the data sheet, Micron’s Web site provides a system power calculator to help calculate MAX power based on system use conditions.
Is the tRC timing parameter asynchronous?
No. You must wait the number of clock cycles that correspond with the tRC value for a given configuration before you issue a command to the same bank. For example, if you are using configuration three, you must wait eight clock cycles before you issue another command to the same bank regardless of the operating frequency.
I’ve heard about the new multibank write feature on RLDRAM 3. What exactly is this feature?
Multibank write is a feature that allows for SRAM-like random read access time. Using this feature can reduce RLDRAM 3’s already low tRC (<10ns) by up to 75% during reads. Through the RLDRAM 3 mode register, you can choose to write to one, two, or four banks simultaneously. By storing identical data in multiple banks, the memory controller has the flexibility to determine which bank to read the data from in order to minimize tRC delay.
I’ve heard you’ll be sampling RLDRAM 3 memory in 2011. Do I need to switch to RLDRAM 3?
Not necessarily. While RLDRAM 3 memory offers several performance advantages over RLDRAM 2 memory (it’s twice as fast), we plan to support RLDRAM 2 for a long time. So there’s no urgent need to roll your design. In fact, our die shrink for RLDRAM 2 memory (also coming in 2011) shouldn’t necessitate a design change for existing customers. Contact your Micron representative if you have questions.
Now that you’re introducing RLDRAM 3 technology, should I be concerned about the lifespan for RLDRAM 2 memory?
No. While we’re developing RLDRAM 3 technology we’re also updating the design for RLDRAM 2 memory, transitioning it to our leading 300mm fabs. This process shrink will reduce power consumption and increase performance for the 288Mb product, but most importantly, it will allow us to support RLDRAM 2 memory well into the next decade.
When can I get RLDRAM 3 memory?
Early RL 3 samples are available now, with qualified (QS) parts expected in fall 2011, and production beginning at the end of 2011. For more information, request an RLDRAM 3 data sheet.
When I upgrade my system memory from 288Mb to 576Mb RLDRAM II, what design considerations do I need to pay attention to?
The 576Mb RLDRAM II device has been designed as a drop-in solution when upgrading from the 288Mb density. Only one additional address pin is needed to support this upgrade. Also, because of the increase in density, the 576Mb device must be refreshed twice as often as the 288Mb device (131,072 refresh commands for the 576Mb device versus 65,536 refresh commands for the 288Mb device every 32ms). The 576Mb device should meet all other existing timing specifications for a comparable 288Mb speed grade.
Which high-speed transceiver logic (HSTL) class do the RLDRAM II DQs comply with?
The RLDRAM II DQs comply both with HSTL class I and HSTL class II because the DQs’ output impedance can be selected to meet the IOH/IOL requirements of each class. The output impedance is selectable when the MRS bit A8 is set HIGH and an external precision resistor is connected to the ZQ pin. Output impedance values of 25–60 ohms can be chosen when a resistor of five times the desired value is placed between the ZQ ball and VSS. For example, a 300 ohm resistor is required for an output impedance of 60 ohms. With the option of using a 1.8V output voltage and programmable output impedance, the RLDRAM II can also operate in an SSTL environment, although it is not compliant with this standard.
Will I be able to leverage any existing DRAM technology to ease the adoption of RLDRAM 3 in my system?
Yes. Even though RLDRAM 3 is a new architecture, it leverages many features from both DDR3 and RLDRAM 2 to make adoption and integration as easy as possible. The command protocol, addressing, and strobing scheme are the same as RLDRAM 2, while the I/O, AC timing, and read training register very closely resemble those found in DDR3.
Are Micron's LPDRAM products green/RoHS compliant?
Yes. Micron’s green engineering program is RoHS-compliant and conforms with most of the world’s emerging environmental standards, including those in Asia and Europe.
Are your LPDRAM parts JEDEC-compliant?
We design our parts to meet or exceed the JEDEC specification. As standards change, we will make the necessary changes to ensure our parts meet new specifications. Any changes made will be noted in a product change notice (PCN) and sent to our customers.
Do you recommend a x8, x16, or x32 configuration for mobile applications?
LPDRAM is offered in x16, x32, and x64. To make the best LPDRAM choice, consider the application, bandwidth/throughput, physical space on the PCB, and power consumption.
Does Micron's LPDRAM cost more than standard DRAM?
It depends. Density plays a major role in price comparisons between LPDRAM and standard SDR/DDR. Also, since LPDRAM is offered in standard configurations of x16, x32 and x64, you may be able to reduce your overall BOM cost if your application currently uses two x16 components to support a x32 bus. You could use one x32 LPDRAM instead of two x16 standard DRAM. Contact your local rep for cost information.
How does LPDDR3 differ from DDR3L-RS?

LPDDR3 is optimized for battery life and portability. DDR3L-RS is a low IDD6 version of the DDR3L die and offers a balance in price versus performance, along with improved standby power.

How does LPDDR3 differ from LPDDR2?

LPDDR3 increases performance to 1600 Mb/s (versus 1066 Mb/s for LPDDR2). Additional changes include write leveling, C/A (command/address) training, and a lower I/O capacitance limit to improve timing.

Is LPDRAM a growing market?
Absolutely. iSuppli estimates that the market for LPDRAM is growing rapidly, with a CAGR of 21.2% from 2006 to 2011. We’re continuing to develop advanced LPDRAM solutions to meet this growing market.
The part I was using is obsolete and the replacement is a faster speed grade. Can I run the LPDRAM parts at a lower speed?
Yes. A LPDRAM part can be run at any speed equal to or slower than its rated speed grade.
What is LPDRAM?
Optimized for products where power consumption is a concern, our low-power LPDRAM devices combine leading-edge technologies and packaging options to meet space requirements and extend battery life. LPDRAM is available with DDR/SDR interface.
What is the life expectancy of Micron's LPDRAM products?
We're excited about this fast-growing market. We plan to manufacture LPDRAM for many years to come and plan to continue to shrink our designs to achieve higher densities.
What LPDRAM parts have been validated on the OMAP35x?
Micron works closely with Texas Instruments (TI) to validate and optimize our parts for the OMAP35x processors. As we work with the OMAP35x team, the list of validated memory devices expands frequently. For the most current information, contact your local Micron support, or contact Micron Product Sales Support.
What makes Micron's LPDRAM unique?
We offer a comprehensive LPDRAM product portfolio, with a wide range of densities and package options (including JEDEC-standard VFBGA, Known Good Die, and package-on-package). With nearly a decade of LPDRAM experience, our worldwide technical support team can provide the expertise and assistance you need to get your designs to market faster.
What’s the difference between Mobile DRAM and LPDRAM?
There is no difference; Mobile DRAM and LPDRAM are the same product. We opted to add the "LP" prefix to our Mobile DRAM product line to align with the common terminology used throughout the industry and to ensure our customers know at a glance that our Mobile DRAM is a low-power memory device. In addition to the family name change, Mobile DDR SDRAM and Mobile SDR SDRAM are now called Mobile LPDDR and Mobile LPSDR, respectively. Our Web site has been wholly converted to the LPDRAM naming convention, but because we’re updating our PDFs as they come up for review you may see a few older technical documents that still use the old Mobile DRAM terminology.
Where are Micron's LPDRAM products used today?
Our LPDRAM products are used in a wide variety of applications. The most popular are consumer electronic devices like digital still cameras and MP3 players, as well as mobile phones and PDAs. Automotive, medical, and military companies, which are very stringent on quality and reliability, use LPDRAM to take advantage of the wide industrial temperature range of –40°C to +105°C, which other memory vendors don’t support. It’s also designed in to a variety of networking applications.