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What are some of the additional power-saving features of DDR4?

Some new power-savings features in DDR4 include pseudo open-drain DQs (for read and write I/O power reduction), data-bit inversion (DBI), and command address latency (CAL).

What is the value of DDR4?

DDR4 has more than 20 new features compared to DDR3, focused on power saving, performance, manufacturability and reliability. These features, coupled with DDR4’s 1.2v core, can provide power savings of 25% compared to standard DDR3. DDR4’s architecture and added performance features offer a substantial performance boost in bandwidth and command scheduling, which can be realized for 100% or better effective bandwidth increase. Premium DDR4 offers over 170% faster max data rates than top-tier DDR3, with speeds as high as 3200MT/s.

Can DDR4 operate at slower DDR3 speeds?

DDR4 is backward compatible as far back as DDR3-1333. For systems that do not need speed increases above DDR3-1333 and DDR3-1600, DDR4 can support these slower bandwidth requirements with substantially lower power requirements.

Where will DDR4 devices be manufactured?

DDR4 will be produced in Micron fabs around the world, including Virginia, Singapore, and Taiwan.

Are there any features on DDR3 that have been eliminated by DDR4?

Not really; however, DDR4 does not require an external VREFDQ, but it does provide an internally generated VREFDQ that requires calibration by the DRAM controller.

Does DDR4 use the same signaling protocol as DDR3?

DDR4 uses the same VTT mid-point termination methodology (SSTL1.5) on the address, command, and control pins as DDR3; however, DDR4 uses VDD termination (POD12) on the data bus due to the use of pseudo open-drain I/Os for improved signal quality and less switching current.

Does DDR4 use the same power sources as DDR3?

No, DDR3 requires VDD and VDDQ equal to 1.5V, VREFCA equal to 0.5 x VDD, and VREFDQ equal to 0.5 x VDDQ, while DDR4 requires VDD and VDDQ equal to 1.2V, VREFCA equal to 0.5 x VDD, and VPP equal to 2.5V.

What is DDR4’s VPP supply, and why does DDR4 have it?

The VPP supply replaces the internal word-line charge pumps. Providing this voltage externally allows the DDR4 to operate at a lower voltage level in a more cost-effective manner rather than providing the internal charge pumps.

Are DDR3 and DDR4 pin-to-pin compatible to each other?

No, the DDR4 ballout is different from the DDR3 ballout. However, DDR4 uses the same package sizes and ball pitch as DDR3.

DDR4 doubled the data rate of DDR3—did the prefetch also double from 8n to 16n?

No, DDR4 kept the 8-bit prefetch used by DDR3; thus, BL8 is still supported.

Did DDR4 finally add boundary-scan or JTAG support?

For x16 devices, yes; DDR4 added a “connectivity test” mode that allows electrical verification of balls after connection to a memory interface.

Are there any new inputs/outputs required to support DDR4?

Yes, seven new inputs/outputs were added: VPP, BG (bank group), DBI_n, ACT_n, PAR, Alert_n, and TEN. However, the ball count increased by only three (73 to 76 balls).

Does DDR4 support DLL off mode for very slow clock rates?

Yes, DDR4 supports DLL-off mode similar to DDR3, up to 125 MHz.

Are the DDR3 voltages backward compatible?

Yes, all of our 1.35V parts are backward compatible with 1.5V.

Can I run Micron’s DDR3 memory at clock speeds slower than 300 MHz?
Yes. Micron supports the optional feature to disable the DLL. This feature allows the DRAM to operate at frequencies slower than 125 MHz. A minimum clock rate is not specified, but the timing still must satisfy the refresh interval (tREFI). When operating in DLL disable mode, special conditions apply: - no support of on-die termination (ODT); ODT must be disabled or turned off - both CL and CWL must be equal to 6 - data out is no longer edge-aligned to the clock and read latency will be AL + CL - 1 tCK
How do I determine my CAS WRITE latency (CWL)?
In DDR3, only one CWL is valid for a given clock frequency range. - tCKavg = 2.5ns to <3.3ns, CWL = 5 - tCKavg = 1.875ns to <2.5ns, CWL = 6 - tCKavg = 1.5ns to <1.875ns, CWL = 7 - tCKavg = 1.25ns to <1.5ns, CWL = 8
How do I determine the amount of time between ZQCS commands?
Each ZQCS command can correct a minimum of 0.5 percent impedance error within 64 clocks. To calculate the ZQCS interval, use the following formula: ZQCS Interval =ZQCorrection (Tsens x Tdriftrate) + (VSens x Vdriftrate) For the sensitivities, use the MAX number from the ODT voltage and temperature sensitivity table in the component specification. Drift rates will vary from system to system. ZQCorrection equals 0.5%/64 clocks.
What component densities are available?
JEDEC has defined DDR3 densities of 512Mb–8Gb; Micron plans to support 1Gb through 4Gb.
What is burst chop?
Due to DDR3's use of the 8n-prefetch architecture, a true burst of 4 is not possible with most designs. Burst chop mode (BC4) is unique to DDR3. In this mode, the last 4 bits of the burst are essentially masked. Timing in BC4 cannot be treated like a true BL4. For READ-to-WRITE, select WRITE-to-READ, and select WRITE-to-PRECHARGE transitions, the system can achieve clock savings in the BC4 mode. While doing READ-to-READ or WRITE-to-WRITE transitions, timing must be treated like BL8; no clock savings will be realized.
What is Dynamic ODT?
Dynamic ODT (Rtt_WR) enables the DRAM to change termination values during a WRITE without having to perform a MODE REGISTER SET command. When Rtt_Wr and Rtt_Nom are both enabled, the DRAM will change termination values from Rtt_Nom to Rtt_Wr at the beginning of the WRITE burst. Once the burst is complete, the termination will be changed back to the Rtt_Nom value. Rtt_Wr can be used independently of Rtt_Nom, but termination will be on WRITEs only.
What is the difference between the ZQCL and ZQCS commands?
ZQCL stands for ZQ calibration long. This command must be issued during the power-up and initialization sequence and requires 512 clocks to complete. After power-up and initialization, the command can be issued any time the DRAM is idle. These subsequent commands only require 246 clocks. This command is used when there is more impedance error correction required than a ZQCS can provide. ZQCS stands for ZQ calibration short. This command can be performed any time the DRAM is idle. One ZQCS can correct a minimum of 0.5 percent impedance error and requires 64 clocks.
What is the "MPR"?
MPR is a multi-purpose register. It is a specialized register designed to allow predefined data to be read out of the DRAM. Data is one bit wide and is output on a prime DQ. For Micron DDR3 parts, the prime DQs are DQ0 for x4/x8 and DQ0/DQ8 for x16. Two locations in the MPR are defined. One allows the readout of predefined data burst—in this case, 01010101. The other location is used to output the refresh trip points from the on-die thermal sensor.
What is the operating voltage?
DDR3 operates at Vdd = VddQ = 1.5V ±0.075V.
What is the output driver impedance for DDR3?
The default output driver impedance for DDR3 is 34 ohms. The impedance is based on calibration to the external 240 ohm resistor, RZQ.
What is the RESET# pin used for?
RESET# is the master reset for the DRAM. It is an active LOW, asynchronous input. When the RESET# is asserted, the DRAM outputs and ODT will tri-state. The DRAM counters, registers, and data will be unknown. A RESET must be performed as part of the power-up and initialization sequence. During this sequence, the RESET# must remain LOW for a minimum of 200µs. After power-up and initialization, RESET# may be asserted at any time. Once asserted, it must stay LOW for a minimum of 100ns and a full initialization of the part must be performed afterward.
What is "write leveling"?
For improved signaling, DDR3 modules have adopted fly-by technology for the commands, addresses, control signals, and clocks. Due to signal routing, this technology has an inherent timing skew between the clock and DQ bus at the DRAM. Write leveling is a way for the system controller to de-skew the DQ strobe (DQS) to clock relationship at the DRAM. A simple feedback feature provided by the DRAM allows the controller to detect the amount of skew and adjust accordingly.
What is "ZQ Calibration"?
The ZQ calibration command can calibrate the DRAM's output drivers (Ron) and ODT values (Rtt) over process, voltage, and temperature when a dedicated 240 ohm (±1 percent) resistor is connected from the DRAM's ZQ pin to ground. In DDR3, two different calibration commands exist: ZQ calibration long (ZQCL) and ZQ calibration short (ZQCS). ZQCL is normally used during power-up initialization and reset sequences, but may be issued at any time by the controller, depending on the system environment. ZQCS is used to perform periodic calibrations to account for small voltage and temperature variations; it requires a smaller timing window to complete.
What termination values does DDR3 offer?
DDR3 supports Rtt_Nom values of 120, 60, 40, 30, and 20 ohms. Dynamic ODT (Rtt_Wr) values are 120 and 60 ohms.
Will Micron support an extended temperature range for DDR3?
Yes. Micron DDR3 parts will support a Tcase of 0°C to 95°C.
Are there any supply voltage savings with 1.5V DDR2 SDRAM versus 1.55V DDR2 SDRAM?
Yes, the 1.5V DDR2 SDRAM uses about 15–20 percent less current than the 1.55V DDR2 SDRAM.
Are there any timing specification differences between 1.5V DDR2 SDRAM and 1.8V DDR2 SDRAM?
Are there any timing specification differences between 1.55V DDR2 SDRAM and 1.8V DDR2 SDRAM?
Yes, DLL-controlled output specs require some derating.
Can DDR2-1066 be used with two slots?
Using DDR2-1066 with two slots is unrealistic; simulations have not shown acceptable margins.
Can you explain how on-die termination (ODT) affects power consumption?
On-die termination (ODT) power is very application-dependent. ODT is also variable, depending on the setting in the EMR of the DRAM. Use the DDR2 power calculator to determine the values.

In a point-to-point system, ODT would only be active on WRITE cycles, and would not consume power during idle and READ cycles. On-board termination would consume power in these instances. ODT power should be about 2–3 percent of the total DDR2 DRAM power in a typical application.
How much power does the Vref power pin draw?
The Vref pin does not draw any power, only leakage current, which is less than 5µA.
Is DDR2-1066 a JEDEC standard?
Not yet, but it’s in process.
Is the ridge down the middle of the underside of FBGA packages conductive?
No, only designated balls are conductive.
Is VREF allowed to float during self refresh mode?
No, it must be maintained at VDDQ/2.
Should DDR2 SDRAM always have ODT turned on?
It’s not recommended, as the SDRAM reads will lose voltage margin; but technically, it is allowed.
Should the DLL be disabled?
Although in some cases the DRAM may work with the DLL off, this mode of operation is not documented nor supported by JEDEC. Therefore, each DRAM design may behave differently when configured to run with the DLL disabled. Micron does not support or guarantee operation with the DLL disabled. Running the DRAM with the DLL disabled may cause the device to malfunction and/or violate some DRAM output timing specifications.
What is the DDR2 RDQS pin for?
The sole purpose of RDQS is to support the use of a x8-based RDIMM in a x4-based RDIMM system. The RDQS pin enables a x8 DDR2 SDRAM to emulate two x4s.
What is the difference between 1.5V DDR2 SDRAM and 1.55V DDR2 SDRAM?
1.5V DDR2 SDRAM is not backward compatible to 1.8V operating systems, and the 1.55V DDR2 SDRAM is.
What is the maximum clock rate for DDR2 when it’s used with a single-ended DQS?
The answer depends mostly on design implementation. As long as the data setup and holds have 150ps or more of margin and there’s a fast slew rate, a single-ended DQS should be OK.
Will the device run at a slow clock (well under the slowest data sheet speed)?
For a READ operation, the DRAM edge-aligns the strobe(s) with the data. Most controllers sense the strobe to determine where the data window is positioned. This fine strobe/data alignment requires that each DRAM have an internal DLL. The DLL is tuned to operate for a finite frequency range, which is identified in each DRAM data sheet. Running the DRAM outside these specified limits may cause the DLL to become unpredictable. The DRAM is tested to operate within the data sheet limits. Micron does not suggest or guarantee DRAM operation outside these predefined limits.
Can CKE be tied HIGH throughout SDRAM operation (initialization and normal operation)?
JEDEC does not specify the exact state of CKE during initialization; it is supplier specific. Micron strongly recommends CKE be kept at an LVTTL logic LOW before applying a stable CLK signal. During normal operation, CKE can be tied HIGH. The initial LOW state of CKE prevents parts from receiving an illegal LMR command, which could put the part into an unknown or unexpected state.
Can the SDRAM clock frequency be changed?
Micron SDRAM data sheets require that the clock frequency be constant during access or precharge states (READ, WRITE, tWR, and PRECHARGE commands). At other times frequency should not matter much because there is no DLL in SDRAM however, we do not recommend it. Lowering SDRAM frequency is OK even if you are not doing an LMR and CAS latency change. In case of increasing frequency, ensure tCK and CAS latency specifications are met. In either case, all other data sheet timing specifications should be adhered to.
Is there a recommended lowest working frequency for SDRAM?
Because SDRAM does not have a DLL, there is no recommended lowest frequency. SDRAM parts will work at very low frequencies if all data sheet specifications are met. It is important to maintain a good slew rate, however, since a very slow slew rate will affect setup and hold-time transitions. Also, for operating frequencies of 45 MHz, tCKS = 3.0ns. For more information, see TN-48-09.
A customer uses a DDR -6T part at 333 MHz. Can he substitute a faster speed grade part (DDR400, -5B) without encountering problems due to the 2.6V operation? Can the customer run the part at -75 speeds?
Yes, all speed grades are backward-compatible. So, -5B can run at -6T timing and -6T voltage levels (2.5V). At DDR400 speeds, Micron parts require (in compliance with JEDEC standard) Vdd = VddQ = 2.6V ±0.1V. At slower speed grades (DDR333 through DDR200), the Micron parts are backward compatible, only requiring Vdd = VddQ = 2.5V ±0.2V.
Can I get samples?
Yes. Talk to your service representative.
Can you provide a brief description of the necessary circuit functionality we would need to employ to transition from EDO to SDRAM technology?
Synchronous DRAM, as its name suggests, is a synchronous device and is a little different from EDO. SDRAM are directly tied to the same system clock that drives all of the other subsystems. SDRAM uses a dual-bank architecture—an interleave technique that essentially allows one cell to be read while another is being prepared for a cell access. This "cell hopping" eliminates downtime between cell activities and provides good performance improvement. Since the SDRAM will operate at higher speeds, attention needs to be paid to signal layout, including transmission line techniques such as series-terminating resistors. A consequence of signal layout could be noise due to faster clocks, crosstalk, etc. At the very least, an SDRAM controller is necessary for transitioning from EDO to SDRAM technology.
Do I need a separate voltage regulator to supply Vref power?
How Vref is supplied depends on the system design. Many multi-drop systems (where there are several modules and a need for Vtt on the system board) already have a designated voltage regulator for DDR memory. In this case, the voltage regulator may have a dedicated tap for Vref. Other systems that incorporate point-to-point memory typically use a simple voltage divider resistor network between Vdd and Vss.
Does Micron provide VHDL models for DDR parts?
No. Micron no longer supports VHDL models. We can, however, provide a generic 8 Meg x 8 model (MT46LC8M8) that can be scaled to the desired model dimensions. It’s a good starting point for building a compatible DDR model. To obtain this file, contact your Micron representative or a Micron applications engineer. You could also contact Denali or Synopsys to obtain one of their models. Or you could use a suitable multi-language simulator (like Modelsim) that cosimulates Verilog and VHDL and then download our Verilog model.
How long does Micron plan to support 3.3V SDRAM?
Micron has an extensive customer base across all four densities (64–512Mb) of SDR and plans to support it for several years. Contact your local Micron sales representative for direction on the preferred part number to qualify.
How long does Micron plan to support DDR?
Micron has an extensive customer base across all four densities (256Mb–1Gb) of DDR and plans to support it for several years. Contact your local Micron sales representative for direction on the preferred part number to qualify.
Is VREF required during self refresh? I would like to put DDR memory in self refresh mode and turn off power to the CPU (the system is battery-operated). Can I disable VREF and still have correct self refresh operation?
Yes. VREF is required during self refresh. All DDR components' on-chip address counters are still operational during self refresh mode, so VDD must be maintained within the stated data sheet limits. Again, VREF must not be disabled after the DDR memory is put into self refresh mode. Doing so could easily result in inadvertently exiting self refresh. You should understand that VREF draws almost no power; any current drawn by VREF is negligible when compared to VTT and the core VDD. DDR components typically use a differential pair common source amplifier as their SSTL_2 input receiver. Because the VREF pin is used primarily as an input to this circuit, its current draw is low. It is so low, in fact, that the device’s input leakage current (~5µA) can be considered the maximum current requirement for the VREF pin. Typical VTT power is drawn from other places on the board and depends on the other components used on the module/system in addition to DRAM devices.
On DDR, can the allowed jitter tolerance be larger than +/-150ps if we use a clock of 120 MHz instead of 133 MHz? Can the allowed jitter tolerance be larger if the device is faster?
The part may have more tolerance or margin to jitter than 150ps at 133 MHz, but Micron still has the same specification for all speeds. Micron does not relax jitter specifications for a lower speed.
On DDR, what happens when DQS write postamble (tWPST) maximum specification is exceeded? What problems could this cause?
The tWPST maximum specification is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly.
On DRAM, can a READ or WRITE command be given instead of a refresh?
If all of the different row addresses are read or written within the refresh time (tREF), a refresh need not be performed. (The different row addresses are the same number of rows as the number of REFRESH cycles. For example, in the case of 8,192/64ms, the number of rows equal 8,192.) With DRAM, selecting row addresses causes the same action as a refresh, so a REFRESH command need not be executed.
On DRAM, can unused DQ (data) pins be left floating?
Micron recommends that unused data pins be tied HIGH or LOW. Because Micron uses CMOS technology in DRAM manufacturing, letting them float could leave the pins susceptible to noise and create a random internal input level. Unused pins can be connected to VDD or ground through resistors.
What is the difference between no connect (NC), no function (NF), and do not use (DNU) pins? How should external connections to them be handled?
An NC (no connect) pin indicates a device pin to which no internal connection is present or allowed. Micron recommends that no external connection be made to this pin. However, if a connection is inadvertently made, it will not affect device operation. Sometimes NC pins could be reserved for future use. Refer to the part’s data sheet to confirm whether the pin is reserved for future use. An NF (no function) pin indicates a device pin that is electrically connected to the device but for which the signal has no function in the device operation. Micron strongly recommends that no external connection be made to this pin. A DNU (do not use) pin indicates a device pin to which there may or may not be an internal connection but to which no external connections are allowed. Micron requires that no external connection be made to this pin. Refer to the part’s data sheet for more details.
What is the maximum junction temperature at which DDR SDRAM functionality is guaranteed?
Please refer to page 3 of Micron’s technical note on thermal applications: TN-00-08. If functionality or operation is not a concern, refer to storage temperature specification limits on the part’s data sheet.
How does Graphics DRAM differ from regular DRAM?
Graphics DRAM is a category of DDR SDRAM designed to handle very large bandwidth requirements. Unlike standard DRAM, graphics DRAM is typically soldered down on the same PCB as the SoC and always supports 32 DQs per memory component. Besides graphics cards and game consoles, graphics DRAM is being used in high-bandwidth applications like networking, automotive and high-performance computing.
What features and functions does GDDR5 have versus previous generations of Graphics DRAM?
GDDR5 provides higher densities, lower external voltage and more than twice the memory bandwidth compared to its predecessor, GDDR3. GDDR5’s 4X relationship between data rate and the CK clock is unique compared to the 2X relationship in DDR3 and GDDR3.
Is GDDR5 a direct replacement for GDDR3?
No, GDDR5 is not a direct replacement for GDDR3 due to package size differences. GDDR3 has a 136-ball BGA package while GDDR5 has a 170-ball BGA package.
How does Graphics DRAM differ from regular DRAM?
Graphics DRAM is a category of DDR SDRAM designed to handle very large bandwidth requirements. Unlike standard DRAM, graphics DRAM is typically soldered down on the same PCB as the SoC and always supports 32 DQs per memory component. Besides graphics cards and game consoles, graphics DRAM is being used in high-bandwidth applications like networking, automotive and high-performance computing.
What features and functions does GDDR5X have compared to previous generations of Graphics DRAM?
GDDR5X provides higher densities and lower external voltage (1.35V) compared to its predecessor, GDDR5. GDDR5X also doubles the bandwidth (10–16 Gb/s) of GDDR5 while remaining on traditional discrete package technology (FBGA).
Can GDDR5X operate in GDDR5-like mode?

Yes, GDDR5X has two operation modes:

  • QDR mode: Supports speeds of 10 Gb/s and above
  • DDR mode: Supports 0.2–6 Gb/s speeds and is compatible with GDDR5
Does GDDR5X support JTAG boundary scan?
Yes, GDDR5X added a connectivity test mode that allows electrical verification of balls after connection to a memory interface.
What is Micron’s competitive position with GDDR5X?
Micron is the first memory supplier in the industry supporting GDDR5X in mass production.
Is GDDR5X a JEDEC standard?
Yes, the GDDR5X SGRAM standard was first published in Dec. 2015 as JESD232. The latest JEDEC release is JESD232A.
Does GDDR5X replace GDDR5?
GDDR5X is not a direct replacement for GDDR5 due to package size differences. GDDR5 has a 170-ball, 0.8mm-pitch BGA package while GDDR5X has a 190-ball, 0.65mm-pitch package.
How does graphics DRAM differ from regular DRAM?
Graphics DRAM is a category of DDR SDRAM designed to handle very large bandwidth requirements. Unlike standard DRAM, graphics DRAM is typically soldered down on the same PCB as the SoC and always supports 32 DQs per memory component. Besides graphics cards and game consoles, graphics DRAM is being used in high-bandwidth applications like networking, automotive and high-performance computing.
What features and functions does GDDR6 have compared to previous generations of graphics DRAM?

GDDR6 provides higher densities than previous-generation graphics memory. It doubles the bandwidth (12–16 Gb/s) of GDDR5 while remaining on the traditional discrete package technology (FBGA). GDDR6 has the same low external voltage (1.35V) as GDDR5X but is based on a dual-channel architecture instead of GDDR5X’s single-channel architecture, which enables a huge performance increase while still providing backward compatibility to GDDR5.

GDDR6 extends the lifespan of the graphics card ecosystem in the follow ways:

  • Uses a cost-efficient, mature assembly process on conventional equipment, resulting in high product reliability and fast time to market
  • Uses a similar BOM structure to GDDR5 and GDDR5X
  • Follows successful path of PCB assembly while enabling system data rates up to 1 TB/s
Can GDDR6 operate in GDDR5-like mode?
Can GDDR6 operate in GDDR5X-like mode?
Does GDDR6 support JTAG boundary scan?
Yes, GDDR6 added a connectivity test mode that allows electrical verification of balls after connection to a memory interface.
What is Micron’s competitive position with GDDR6?
Micron is leveraging its GDDR5X-based high-speed signaling know-how from more than two years of design, mass production, test and application learning in Micron GDDR6 products. This allows Micron to remain in the leading position on high-speed signaling with traditional memory components.
Is GDDR6 a JEDEC standard?
Yes, the GDDR6 SGRAM standard was first published in July 2017 as JESD250.
Does GDDR6 replace GDDR5 or GDDR5X?
GDDR6 is not a direct replacement for GDDR5 nor GDDR5X due to package size differences. GDDR5 has a 170-ball, 0.8mm-pitch BGA package, GDDR5X has a 190-ball, 0.65-mm pitch BGA package and GDDR6 has a 180-ball, 0.75mm-pitch BGA package.
Are CK/CK# and DK/DK# true differential inputs?
Yes, the CK/CK# and DK/DK# input buffers are true differential inputs. Both sets of clocks need to meet the specifications that are defined in the Clock Input Operating Conditions tables in the RLDRAM II memory data sheets.
Are there any new features in RLDRAM 3 not found in earlier generations of the RLDRAM product line?
Yes. Multibank write is a new feature that enables SRAM-like random read capabilities. Managing refresh overhead is now more flexible than ever with the addition of the MULTIBANK REFRESH command. With this command, you can refresh one to four banks simultaneously. We’ve also added a mirror function ball to ease layout of clamshell designs. Depending upon the state of the mirror function ball, the command and address functions are swapped across the y-axis to allow for direct connections through the PCB.
Can 2.5V or 3.3V be directly input to joint test action group (JTAG) pins?
No. The highest operating voltage that can be input to the JTAG pins is VDD + 0.3V as outlined in the TAP DC Electrical Characteristics and Operating Conditions tables in the RLDRAM II data sheets.
Can I connect the “Do Not Use” (DNU) pins to ground (GND)?
Yes. However, when on-die termination (ODT) is enabled, the DNU pins will be connected to VTT. Connecting the DNU pins to GND under these circumstances will cause a substantially larger load on your VTT supply.
Can I reload the mode register after I have been operating with READs and WRITEs on RLDRAM II memory?
Yes, the mode register can be reloaded at any time as long as all timing specifications are met. Burst length must be considered, however. If the burst length is changed, previously written data will be corrupted.
Can RLDRAM II run slower than 175 MHz?
Yes, but the DLL must be turned off. With the DLL turned off, the output data alignment with the CK will shift by about 3–4ns, which works like the outputs of RLDRAM I memory.
Does the 576Mb RLDRAM II device still support 1.8V VDDQ? Is it possible to run at 533 MHz with VDDQ = 1.8V?
It should not be a problem to run at 533 MHz with VDDQ = 1.8V. Micron has run graphics devices at 800 MHz clock at 1.8V.
Does the RLDRAM internally compensate for voltage and temperature changes when bit A8 is not selected HIGH on the RLDRAM II during setting of the mode register?
Yes. When bit A8 of the mode register is HIGH, the user places an external precision resistor between ZQ and VSS to select an output impedance. When bit A8 is LOW, the output impedance is set to 50 ohms (±30 percent). In both cases, however, the RLDRAM device periodically calibrates this impedance to compensate for shifts in voltage and temperature. This calibration is internal to the RLDRAM and does not affect the operation of the RLDRAM.
During initialization, are 2,048 clock cycles really needed between each AUTO REFRESH command?
No. Although it is still outlined in some older data sheet revisions, it is not necessary. During initialization, it is necessary for all eight banks to receive an AUTO REFRESH command tMRSC after the last valid MRS command has been issued. If you sequentially issue AUTO REFRESH commands instead of waiting 2,048 clock cycles between each command, you must perform at least 1,024 NOP commands between the last AUTO REFRESH command and the first valid command in normal operation. Either method will satisfy the requirements of the RLDRAM.
During power-up, I bring VDDQ HIGH before VDD. Will this cause a problem?
The RLDRAM II will not be adversely affected if you bring VDDQ HIGH before VDD. However, you must be aware that when you perform the sequence in this way, the DQs, DM, and all other pins with an output driver will go HIGH instead of tri-stating. These pins will remain HIGH until VDD is at the same level as VDDQ. Care should be taken to avoid bus conflicts during this period.
How can I reset the RLDRAM II device?
RLDRAM II memory can be reset using the MODE REGISTER command. Three MRS commands must be issued on consecutive clock cycles to reset the device properly. If any commands (including NOP commands) are issued between the MRS commands, the device will not be reset.
How is RLDRAM II memory similar to SRAM?
RLDRAM II memory is similar to SRAM in a variety of ways: - Simplified command set: only four commands (READ, WRITE, REFRESH, and MODE REGISTER SELECTION) - Row/columns not apparent: can clock in the full address in one clock cycle (or can be multiplexed like a standard DRAM) - Fast cycle time: 20ns tRC for the 288Mb device and as low as to 15ns tRC for the 576Mb device
I’m seeing substantial jitter on my outputs; what can I do to remedy this?
A number of things can cause jitter on RLDRAM II memory outputs. Read through the questions below to help identify the cause of the jitter. - Is the same amount of jitter seen at the DQs, QKs, and QVLD signal? If so, the jitter may be due to the DLL. The DQs, QKs, and QVLD all use the DLL to clock out their data. Micron can assist with additional debugging to determine whether any parameters are being violated that would cause the DLL to operate improperly.
- Is there jitter on the input clocks? Any jitter on CK/CK# will be transferred to the outputs.
- Does the amount of jitter change substantially with different output data? If it does, phenomena such as ISI, SSO, or crosstalk could be causing the jitter.
- Is the system properly terminated? Because proper termination is dependent on system parameters, simulation is the best way to determine termination requirements. Micron offers several tools and technical notes to assist with termination requirements:
1.“TN-49-02: Exploring the RLDRAM II Feature Set” includes descriptions and examples of data-eyes when using the on-die termination and impedance-matching features.
2. Technical notes TN-46-14 and TN-46-06 do not specifically mention RLDRAM II memory, but they have useful information about termination and techniques to ensure good signal integrity.
3. The RLDRAM Memory Part Catalog contains configuration information for IBIS and HSpice models.
I’m using RLDRAM memory. Is it possible to tie VDD and VDDQ to the same supply?
Yes. You can tie VDD and VDDQ to the same supply.
Is MAX power specified in the data sheet?
Yes, MAX power is specified in the data sheet. Because MAX power is entirely dependent on how the devices are used in a system, the power must be calculated based on information found in the data sheet. In addition to the information found in the data sheet, Micron’s Web site provides a system power calculator to help calculate MAX power based on system use conditions.
Is the tRC timing parameter asynchronous?
No. You must wait the number of clock cycles that correspond with the tRC value for a given configuration before you issue a command to the same bank. For example, if you are using configuration three, you must wait eight clock cycles before you issue another command to the same bank regardless of the operating frequency.
I’ve heard about the new multibank write feature on RLDRAM 3. What exactly is this feature?
Multibank write is a feature that allows for SRAM-like random read access time. Using this feature can reduce RLDRAM 3’s already low tRC (<10ns) by up to 75% during reads. Through the RLDRAM 3 mode register, you can choose to write to one, two, or four banks simultaneously. By storing identical data in multiple banks, the memory controller has the flexibility to determine which bank to read the data from in order to minimize tRC delay.
I’ve heard you’ll be sampling RLDRAM 3 memory in 2011. Do I need to switch to RLDRAM 3?
Not necessarily. While RLDRAM 3 memory offers several performance advantages over RLDRAM 2 memory (it’s twice as fast), we plan to support RLDRAM 2 for a long time. So there’s no urgent need to roll your design. In fact, our die shrink for RLDRAM 2 memory (also coming in 2011) shouldn’t necessitate a design change for existing customers. Contact your Micron representative if you have questions.
Now that you’re introducing RLDRAM 3 technology, should I be concerned about the lifespan for RLDRAM 2 memory?
No. While we’re developing RLDRAM 3 technology we’re also updating the design for RLDRAM 2 memory, transitioning it to our leading 300mm fabs. This process shrink will reduce power consumption and increase performance for the 288Mb product, but most importantly, it will allow us to support RLDRAM 2 memory well into the next decade.
When can I get RLDRAM 3 memory?
Early RL 3 samples are available now, with qualified (QS) parts expected in fall 2011, and production beginning at the end of 2011. For more information, request an RLDRAM 3 data sheet.
When I upgrade my system memory from 288Mb to 576Mb RLDRAM II, what design considerations do I need to pay attention to?
The 576Mb RLDRAM II device has been designed as a drop-in solution when upgrading from the 288Mb density. Only one additional address pin is needed to support this upgrade. Also, because of the increase in density, the 576Mb device must be refreshed twice as often as the 288Mb device (131,072 refresh commands for the 576Mb device versus 65,536 refresh commands for the 288Mb device every 32ms). The 576Mb device should meet all other existing timing specifications for a comparable 288Mb speed grade.
Which high-speed transceiver logic (HSTL) class do the RLDRAM II DQs comply with?
The RLDRAM II DQs comply both with HSTL class I and HSTL class II because the DQs’ output impedance can be selected to meet the IOH/IOL requirements of each class. The output impedance is selectable when the MRS bit A8 is set HIGH and an external precision resistor is connected to the ZQ pin. Output impedance values of 25–60 ohms can be chosen when a resistor of five times the desired value is placed between the ZQ ball and VSS. For example, a 300 ohm resistor is required for an output impedance of 60 ohms. With the option of using a 1.8V output voltage and programmable output impedance, the RLDRAM II can also operate in an SSTL environment, although it is not compliant with this standard.
Will I be able to leverage any existing DRAM technology to ease the adoption of RLDRAM 3 in my system?
Yes. Even though RLDRAM 3 is a new architecture, it leverages many features from both DDR3 and RLDRAM 2 to make adoption and integration as easy as possible. The command protocol, addressing, and strobing scheme are the same as RLDRAM 2, while the I/O, AC timing, and read training register very closely resemble those found in DDR3.
Are Micron's LPDRAM products green/RoHS compliant?
Yes. Micron’s green engineering program is RoHS-compliant and conforms with most of the world’s emerging environmental standards, including those in Asia and Europe.
Are your LPDRAM parts JEDEC-compliant?
We design our parts to meet or exceed the JEDEC specification. As standards change, we will make the necessary changes to ensure our parts meet new specifications. Any changes made will be noted in a product change notice (PCN) and sent to our customers.
Do you recommend a x8, x16, or x32 configuration for mobile applications?
LPDRAM is offered in x16, x32, and x64. To make the best LPDRAM choice, consider the application, bandwidth/throughput, physical space on the PCB, and power consumption.
Does Micron's LPDRAM cost more than standard DRAM?
It depends. Density plays a major role in price comparisons between LPDRAM and standard SDR/DDR. Also, since LPDRAM is offered in standard configurations of x16, x32 and x64, you may be able to reduce your overall BOM cost if your application currently uses two x16 components to support a x32 bus. You could use one x32 LPDRAM instead of two x16 standard DRAM. Contact your local rep for cost information.
How does LPDDR3 differ from DDR3L-RS?

LPDDR3 is optimized for battery life and portability. DDR3L-RS is a low IDD6 version of the DDR3L die and offers a balance in price versus performance, along with improved standby power.

How does LPDDR3 differ from LPDDR2?

LPDDR3 increases performance to 1600 Mb/s (versus 1066 Mb/s for LPDDR2). Additional changes include write leveling, C/A (command/address) training, and a lower I/O capacitance limit to improve timing.

Is LPDRAM a growing market?
Absolutely. iSuppli estimates that the market for LPDRAM is growing rapidly, with a CAGR of 21.2% from 2006 to 2011. We’re continuing to develop advanced LPDRAM solutions to meet this growing market.
The part I was using is obsolete and the replacement is a faster speed grade. Can I run the LPDRAM parts at a lower speed?
Yes. A LPDRAM part can be run at any speed equal to or slower than its rated speed grade.
What is LPDRAM?
Optimized for products where power consumption is a concern, our low-power LPDRAM devices combine leading-edge technologies and packaging options to meet space requirements and extend battery life. LPDRAM is available with DDR/SDR interface.
What is the life expectancy of Micron's LPDRAM products?
We're excited about this fast-growing market. We plan to manufacture LPDRAM for many years to come and plan to continue to shrink our designs to achieve higher densities.
What LPDRAM parts have been validated on the OMAP35x?
Micron works closely with Texas Instruments (TI) to validate and optimize our parts for the OMAP35x processors. As we work with the OMAP35x team, the list of validated memory devices expands frequently. For the most current information, contact your local Micron support, or contact Micron Product Sales Support.
What makes Micron's LPDRAM unique?
We offer a comprehensive LPDRAM product portfolio, with a wide range of densities and package options (including JEDEC-standard VFBGA, Known Good Die, and package-on-package). With nearly a decade of LPDRAM experience, our worldwide technical support team can provide the expertise and assistance you need to get your designs to market faster.
What’s the difference between Mobile DRAM and LPDRAM?
There is no difference; Mobile DRAM and LPDRAM are the same product. We opted to add the "LP" prefix to our Mobile DRAM product line to align with the common terminology used throughout the industry and to ensure our customers know at a glance that our Mobile DRAM is a low-power memory device. In addition to the family name change, Mobile DDR SDRAM and Mobile SDR SDRAM are now called Mobile LPDDR and Mobile LPSDR, respectively. Our Web site has been wholly converted to the LPDRAM naming convention, but because we’re updating our PDFs as they come up for review you may see a few older technical documents that still use the old Mobile DRAM terminology.
Where are Micron's LPDRAM products used today?
Our LPDRAM products are used in a wide variety of applications. The most popular are consumer electronic devices like digital still cameras and MP3 players, as well as mobile phones and PDAs. Automotive, medical, and military companies, which are very stringent on quality and reliability, use LPDRAM to take advantage of the wide industrial temperature range of –40°C to +105°C, which other memory vendors don’t support. It’s also designed in to a variety of networking applications.
DRAM Modules(3)
Can Vtt and Vref be supplied by the same supply in my system design?
With proper decoupling this can be an acceptable design. However, Micron recommends ensuring all supplies are separated. Vref tends to have more noise on it because it supplies signals that are regularly switching. A robust design would typically not connect these supplies due to the possibility of introducing this noise onto the Vtt plane which should be as stable as possible. Additionally, Vref requires much less current than Vtt.
Is there a set of trace lengths and routing rules that are standard for use when designing a system that uses a specific module technology and form factor?
No. A robust memory subsystem design that includes the use of 1 or more memory modules must be simulated in order to determine the optimum trace lengths, terminations. However, our design guides such as TN-47-01 and TN-41-08 have some best practices and design examples based on some typical system assumptions. This information is not meant to be the only way your system can be designed. It is a starting point and moreover an example of the steps used to determine the best design for your system.
What is NVDIMM?

NVDIMM is a nonvolatile persistent memory solution that combines NAND flash, DRAM and an optional power source into a single memory subsystem. Micron’s NVDIMM is capable of delivering the performance levels of DRAM combined with the persistent reliability of NAND, ensuring data stored in-memory is protected against power loss.

How do NVDIMMs work?

NVDIMMs operate in the DRAM memory slots of servers to execute workloads at DRAM speeds. In the event of a power fail or system crash, an onboard controller safely transfers data stored in DRAM to the onboard nonvolatile memory, thereby preserving the data that would otherwise be lost. When the system stability is restored, the controller transfers the data from the NAND back to the DRAM, allowing the application to efficiently pick up where it left off.

What is persistent memory?

Persistent memory is a new addition to the memory/storage hierarchy that enables greater flexibility in data management by providing nonvolatile, low-latency memory closer to the processor. Essentially, persistent memory accelerates application performance by removing what otherwise are constricting I/O bottlenecks placed on the application by standard storage technologies. By placing nonvolatile memory on the DRAM bus, this architecture enables customers to significantly optimize data movement in order to deliver faster access to variables stored in DRAM.

With persistent memory, system architects are no longer forced to sacrifice latency and bandwidth when accessing critical data that must be preserved. Critical data can be stored close to the processor, dramatically cutting access times. Persistent memory delivers a unique balance of latency, bandwidth, capacity and cost, delivering ultra-fast DRAM-like access to critical data and enabling system designers to better manage overall costs.

What are the key use cases for NVDIMM?

Any application where performance depends on variables stored in nonvolatile media (HDD or SSD) can benefit from NVDIMMs (most applications can be accelerated). Persistent variables include metadata logs, checkpoint state, host write caches, write buffers, journals and general logs. Applications that can be accelerated by placing these variables in NVDIMM include 2-node, high-availability storage using RAID cards, SSD mapping, RAMDisk and write caching for SSDs.

What products are available today?

Micron will be offering three DDR4 NVDIMM products:

  1. 8GB DDR4 NVDIMM with legacy firmware
  2. 8GB DDR4 NVDIMM with JEDEC firmware
  3. PowerGEM® ultracapacitor for 8GB NVDIMM
What is the difference between the legacy and JEDEC firmware?

Legacy firmware refers to the firmware features and controller register locations for features determined by AgigA Tech, Inc., for initial DDR4 NVDIMM designs. JEDEC has now standardized the NVDIMM firmware features, register locations and APIs so that one vendor’s NVDIMM can be compatible with any other vendor’s NVDIMM. All new Micron NVDIMM solutions will leverage the JEDEC firmware interface.

How will NVDIMMs be enabled? What platforms support NVDIMM?

Many motherboards, servers and storage appliances support NVDIMMs today. Many more will come to market in 2016. Contact your supplier for more details.

Are there software requirements for NVDIMM?

NVDIMMs leverage either block mode or direct access drivers. NVDIMMs used in conjunction with a block mode driver are compatible with OS and applications with little to no necessary software modifications. Additional performance capability can be tapped by leveraging an NVDIMM with a direct mapped driver, but OS and application software will likely need some modification. Micron is currently working with major OEMs and software companies to incorporate NVDIMM hardware, driver and software support into their mainstream products.

NAND Flash(19)
How do I achieve greater program/read throughput with a ClearNAND device?
You need to operate at the fastest supported timing mode to get the maximum program/read throughput with Micron ClearNAND Flash. For Standard ClearNAND devices, use multiplane operations wherever possible; for Enhanced ClearNAND devices, issue queued commands via the enhanced command set to improve the device throughput. See the ClearNAND device data sheet for details on how to use these commands.
I am seeing a lot of read disturb errors. Can you tell me if there is a problem with your part?
Read disturb occurs when the same data is read repeatedly. By its nature, NAND technology has a very low occurrence of read disturb errors. However, to mitigate any errors received due to read disturb, we recommend refreshing the data to reduce the amount of times the same data is read.
What types of errors occur with ClearNAND devices compared to traditional NAND?
ClearNAND devices offer additional reliability compared to traditional NAND due to internal ECC, though the same types of errors are present. The host controller can determine whether blocks should be retired or data should be refreshed by monitoring the device status registers following each operation. Additional Micron NAND Flash technical information can be found on the NAND Flash Technical Notes page.
Where can I find simulation models for ClearNAND Flash devices?
Micron posts Verilog, HSpice, and IBIS models for NAND devices. To find the right model for your needs, see the appropriate NAND part catalog and select your device to view the available models.
Why doesn't the ClearNAND Flash device respond correctly to commands issued to it?
Be sure you are issuing a RESET command (FFh) to the NAND device after powering on the device. A RESET command (FFh) must be issued to each valid chip enable (CE#) of the NAND device before any commands are allowed to be issued to that CE#.
Will ClearNAND Flash require new types of controllers?
Standard ClearNAND devices can be used with existing controllers if the controllers support the ONFI 2.3 EZ NAND specification. To take full advantage of the capabilities of our Enhanced ClearNAND device, controllers will need to support the latest ONFI industry standard and incorporate the enhanced command sequences detailed in the device data sheet.
What is e.MMC?

Embedded MultiMediaCard (e.MMC) is a NAND Flash-based memory solution defined by JEDEC that comes in a small BGA package. JEDEC defines both the hardware and software, enabling easy customer design-in and the ability to multisource.

What are the benefits of e.MMC?

e.MMC is a fully managed solution (all media management and ECC are handled internally), making NAND technology transitions invisible to the host and providing customers with the ability to reduce their time-to-market and to sustain products longer and more easily.

What does the term "broad market" signify?

Our embedded market e.MMC products are divided into two families: automotive and broad market. This is due to the unique requirements that are required in the automotive market; thus, there is a separate product line supported by Micron’s automotive team. Broad market covers all other market segments such as consumer, gaming, server, networking, industrial, medical, military, etc. Broad market e.MMC includes two sub-families: WT with commercial temperature grade and IT with an extended temperature range.

How can I order samples?

You can order samples through the Micron Sample Center.

Is it necessary to refer to the JEDEC specification as well as to Micron’s data sheet?

Yes, the JEDEC specification has to be read in conjunction with the data sheet. Micron e.MMC complies with the JEDEC standard; hence, Micron's data sheets provide information that is specific only to Micron’s e.MMC devices.

The JEDEC specification (Standard No. 84-A441) is available at: www.jedec.org/sites/default/files/docs/JESD84-A441.pdf

Are simulation models available?

Yes, IBIS models are available for WT and IT products (JEDEC 153-/169-ball and 100-ball); functional models (such as Verilog) are under evaluation.

What is the e.MMC offering for industrial applications?
Micron is offering an extensive number of solutions for industrial customers, such as five densities and JEDEC-standard BGA 153-/169-ball and custom 100-ball packaging. All of these products will operate in the extended temperature range of -40° to 85°C.
What are the advantages of 100-ball IT e.MMC?

Micron’s 100-ball e.MMC BGA package features a 1.0mm ball pitch for board routing simplification (saving PCB costs) and improved board-level reliability (temp cycling). This solution is particularly attractive to automotive, industrial, and networking market segments. See the following table for additional benefits.

Features of 100-ball e.MMC


Large 1.0mm ball pitch

  • Allows for low-cost PCB trace/space designs
  • Simplifies PCB routing
  • Enables a reduction in the number of PCB layers
  • Reduces costs via a lower drill size
  • Lower DAR (drill aspect ratio) for better PCB yields
  • Allows for wider traces for better thermal dissipation

Large 0.45mm nominal ball diameter

  • Provides high PCB board-level reliability
  • Improves surface-mount yields (vs. smaller ball packages)
  • Provides better thermal dissipation

Low ball count (compared to 153-ball e.MMC JEDEC-standard)

  • Allows for easier, low-cost PCB routing
  • Reduces package and PCB costs

100-ball pattern contains 12 mechanical support balls (3 in each corner)

  • Provides excellent PCB board-level reliability
  • Allows for flexible “large package size” variations

Flexible ball-out design

  • Allows for future e.MMC feature upgrades and next-generation technology
Is Micron the only provider of 100-ball IT e.MMC?

Greenliant Systems offers pin-compatible 100-ball IT e.MMC for those customers requiring a second source. The NANDrive GLS85VM e.MMC product family supports the JEDEC 4.4 standard and operates at full industrial temperature of -40°C to +85°C. The product line is targeted for industrial and the broad market. For further information and support contact: www.Greenliant.com.

Does Micron's e.MMC support SPI mode?

Micron’s e.MMC 4.41 products are compliant to the JEDEC standard. JEDEC removed this feature when introducing the e.MMC 4.3 specification; therefore, SPI mode is not supported. 

Is v. 4.41 e.MMC functionality backward-compatible to v. 4.3?
Yes, v. 4.41 functionality is backward-compatible with v. 4.3; a v. 4.41 e.MMC device will work with a v. 4.3 or v. 4.4 MMC host. The v. 4.41 devices support additional features such as boot and RPMB partitions, high-priority interrupt, background operation, write reliability, and enhanced reliable write.
How can I migrate from Micron e.MMC 4.4 to 4.41?

Micron has EOL’d its e.MMC 4.4 offering. Refer to your AE for support. A dedicated technical note “TN-FC-08: Migrating from Micron v. 4.4 e.MMC to 4.41 e.MMC” is available for review.

Is it possible to perform a system boot from e.MMC?

Yes, e.MMC provides two boot partitions to provide fast access to boot code for improved system boot time. Booting from boot partitions can provide access to stored data in ~50ms, whereas booting from the user area can take hundreds of milliseconds. However, in order to utilize the boot partitions, the chipset must be able to support booting from the boot partition. Check with your chipset vendor to understand if booting from the e.MMC boot partitions is supported.

For more information, refer to “TN-FC-06: Booting from Embedded MMC - JEDEC 4.41.

Does Micron e.MMC support power-loss protection?

Yes, ESG e.MMC devices support static data protection. Devices are shipped from Micron factories as COMBO with a configuration optimized for best write performance. Customers can reconfigure the devices to protect static (previously written) data if there is power loss during a write operation.

What are the enhanced technology features mentioned in JEDEC specification, and what are the benefits?

A part or all of the MLC user space can be configured as pseudo-SLC. The partition offers better reliability, endurance, and performance compared to MLC NAND.

Can I set up partitions within e.MMC to suit different usage models?

The e.MMC specification allows customers to configure the user data area into a maximum of four separate partitions that can each be configured as MLC (default) or enhanced mode (pSLC). Enhanced mode provides better reliability in exchange for twice the space as MLC.

For more information refer to "TN-FC-40: Embedded e.MMC Configuration"

What is the required software support for e.MMC?

e.MMC drivers are generally available on the market due to the fact that it is an industry-standard product.

The e.MMC v. 4.41 standard provides performance, security, and reliability features such as high-priority interrupt and secure erase. These features, such as secure erase and secure trim, require software support from the file system beyond the driver, without which the application call will not reach the storage media via the file system.

Linux supports e.MMC and allows the integration within its subsystems and the Android file system. The advanced features introduced by the JEDEC specification have been supported by patches initially and have only very recently been included in the kernel. See Micron technical note TN-52-05 for details about e.MMC Linux enablement for new features by JEDEC 4.4–4.41.

Proprietary software solutions are available on the market as well.

What is eUSB?
The embedded universal serial bus (eUSB) is a NAND flash-based memory solution that is compliant with the USB industry standards. USB is a widely adopted interface used across multiple platforms and operating systems, providing a low-cost, efficient data transfer solution for current applications and beyond.
What are the benefits of eUSB?

eUSB is a fully managed solution that utilizes NAND memory and, through an onboard controller, internally handles all media management and ECC control. The eUSB provides customers with a complete storage solution that easily integrates into their system and, in turn, fuels a reduced time to market.

Using native SLC NAND memory, combined with a rich set of management features such as global wear leveling and dynamic data refresh, eUSB offers a superior combination of performance and reliability.

How does the eUSB attach to my system board?
The eUSB device has a 10-pin (2x5) USB female connector compatible with the industry-standard 10-pin connector found on most motherboards. A mounting hole (connected directly to internal ground) is also provided on the PCB to ensure a stable connection to the system board.  Additional holes in the PC board, utilized during manufacturing for de-paneling, can also be used as additional mounting locations if required.
Can I use the eUSB as a boot device?
Yes. Micron’s eUSB can be used as the operating system boot and main storage device. However, the application’s BIOS must support the boot mode feature, which should not be a concern for most systems that were manufactured in the last five years and support USB 2.0. In either the main storage or boot mode, the eUSB should be recognized as a fixed hard drive in the system.
Does Micron offer the eUSB with a 3.3V option?
Yes. Please check the part catalog for Micron’s current eUSB offerings.
Does Micron provide a way for me to determine the useful life remaining on the device?
Our latest generation eU500, eUSB 3.1 products do provide a method to extract relevant lifetime data through the use of SMART commands. However, previous generations of eUSB products do not support a runtime method to collect lifetime data.
Is eU500 (eUSB 3.1) fully backward compatible with e230 (eUSB 2.0)?
Yes. Micron’s latest generation eU500 eUSB 3.1 products are backward compliant with the USB 2.0 protocol. The eU500 family also supports the same form factor, voltages and connector offerings as the previous generation e230. Please check the part catalog for Micron’s current eUSB offerings.
3D NAND(4)
Why is 3D NAND necessary?
Planar NAND flash memory is nearing its practical scaling limits, which poses challenges for the memory industry.  Industry innovation requires state-of-the-art NAND technology that scales with higher densities and lower cost per bit. 3D NAND allows flash storage solutions to continue aligning with Moore’s Law, bringing significant improvements in density while lowering the cost of NAND flash.
What sets apart this 3D NAND from other offerings in the industry?

The 3D NAND technology developed by Intel and Micron offers significant improvements in density and cost, and it’s the first 3D NAND to use floating gate cells.  This 3D NAND enables flash devices with three times higher capacity than other planar NAND die in production, and the first generation is architected to achieve better cost efficiencies than planar NAND. There are also various features that will improve latency, increase endurance and make system integration easier.

Micron’s 3D is a “smarter” NAND technology. What do you mean?
We have integrated various features to deliver improved performance and new functionality, including new programming algorithms and power management modes that help make system integration easier. See FortisFlash to learn more about these features.
What are the details of your cell and process technology for 3D NAND?
The new 3D NAND technology uses floating gate cells and stacks flash cells vertically in 32 layers to achieve 256Gb multilevel cell (MLC) and 384Gb triple-level cell (TLC) die that fit within a standard package.
Do you support small block devices?
Currently, Micron only offers large block devices. For more information, please refer to Technical Note, TN-29-07: Small Block vs. Large Block NAND Devices.
How do I achieve greater PROGRAM/READ throughput for the NAND device?
To get the maximum PROGRAM/READ throughput for Micron NAND Flash devices, use the PROGRAM and READ CACHE operations. See the NAND device data sheet and our NAND Technical Notes Page for details on how to use these commands.
How is High-Speed NAND different from traditional NAND?
High-Speed NAND can read data at speeds up to 200 megabytes per second (MB/s) and can write data at speeds up to 100 MB/s. These speeds are achieved by leveraging the new ONFI 2.0 interface specification and a four-plane architecture with higher clock speeds. In comparison, conventional SLC NAND is limited to 40 MB/s for reading data and less than 20 MB/s for writing data. To maximize the performance benefits of High-Speed NAND, users must use the new ONFI 2.0 synchronous interface standard.
How is Nvb specified?
Nvb is specified as the minimum number of valid blocks at the end of the P/E cycle spec.
How much ECC do I need to support your devices?
We define our ECC requirement per 512-byte section. MLC NAND devices have a higher ECC requirement than SLC NAND due to the increased number of bits per cell. ECC requirements differ for designs, so consult the device data sheet for the amount of ECC needed.
I am seeing a lot of READ DISTURB errors. Can you tell me if there is a problem with your part?
READ disturb occurs when the same data is read repeatedly. By its nature, NAND technology has a very low occurrence of read-disturb errors. But, to mitigate any errors received due to read disturb, we recommend that users refresh the data to reduce the amount of times the same data is read.
I am using the correct amount of error correction code (ECC) for the NAND device, but I’m still seeing bit/byte errors in data I read back from the NAND device.
Make sure that you are issuing a READ STATUS command to the NAND device after any type of PROGRAM or ERASE operation. Checking status after a PROGRAM or ERASE operation will report whether the PROGRAM or ERASE operation was successful. If the READ STATUS command reports a failure with a PROGRAM operation, that data should be programmed somewhere else and the block being programmed should be retired. If the READ STATUS command reports a failure with an ERASE operation, that block should also be retired.
I’ve heard that NAND has too many errors to boot from. Is this true?
With ECC, NAND can achieve bit error rates (BER) that are comparable with NOR, which is commonly used as a booting device. Applications that use NAND typically copy the booting code to DRAM and execute from DRAM. For more information, read Tech Note 29-16, which is geared to a specific processor, but the concepts can be applied generally. TN-29-19 is a very useful technical note on the general concepts of NAND.
Should I be marking blocks bad due to READ errors?
What NAND parts have been validated with the OMAP35x?
Micron works closely with Texas Instruments (TI) to validate and optimize our parts for the OMAP35x processors. As we work with the OMAP35x team, the list of validated memory devices expands frequently. For the most current information, contact your local Micron support.
When I issue a Read ID command (90h) to a two-die NAND device, I get a device ID back that states it is a one-die NAND device.
In a two-die NAND device, where a single die is on each CE#, the device ID that is returned is per CE# for one die. For example, an 8Gb two-die NAND device with two CE# pins would return a 4Gb device ID on each CE#. See the Read ID section of the NAND device data sheet for more details.
Where can I find additional technical information about Micron NAND devices that is not covered in the device data sheets?
Additional Micron NAND Flash technical information—including details on performance enhancing commands—can be found on the Technical Notes page for NAND.
Where can I find simulation models for NAND Flash devices?
Micron posts Verilog, HSPICE, and IBIS models for NAND devices. To find the right model for your needs, see the appropriate NAND part catalog and select your device to view the available models.
Why am I getting a bit/byte error reading back the information I programmed into the NAND device?
Check that you are using the appropriate amount of error correction code (ECC) for the NAND device. The ECC threshold can be found in the "Error Management" section of the NAND device data sheet. Also ensure that none of the bad blocks marked by the NAND manufacturer (Micron) are used. See the "Error Management" section of the NAND device data sheet for more details on how to search for manufacturer-marked bad blocks.
Why doesn't the NAND Flash device respond correctly to commands issued to it?
Be sure you are issuing a reset command (FFh) to the NAND device after powering on the device. A reset command (FFh) must be issued to each valid chip enable (CE#) of the NAND device before any commands are allowed to be issued to that CE#.
Hybrid Memory Cube(2)
Short-Reach HMC(13)
What problem does HMC solve?

Over time, memory bandwidth has become a severe bottleneck to optimal system performance. Conventional memory technologies are not scaling with Moore’s Law; therefore, they are not keeping pace with the increasing performance demands of the latest microprocessor and application-specific integrated circuit (ASIC) roadmaps. Microprocessor and ASIC enablers are doubling cores and threads per core to greatly increase performance and workload capabilities. They are doing this by distributing work sets into smaller blocks among an increasing number of work elements (cores). Multiple compute elements per processor require an increasing amount of memory accesses per element. The term “memory wall” has been used to describe this dilemma. With performance levels that break through the memory wall, HMC is a revolutionary technology that enables greater performance for next-generation computing and high-speed networking systems.

Why are current DRAM technologies unable to fully solve this problem?

Current memory technology roadmaps do not provide sufficient performance to optimally meet the CPU, GPU, and ASIC memory bandwidth requirements. By advancing past the traditional DRAM architecture, HMC is establishing a new standard of memory to match the advancements of CPU, GPU and ASIC roadmaps. HMC offers system designers optimum flexibility in developing next-generation system architecture.

What makes HMC so different?

With performance levels that break through the memory wall, HMC unlocks a myriad of  system performance advancements for the next generation of high-performance computing and advances network capabilities to support 100Gb and 400Gb system development.

HMC represents a fundamental change in memory construction and connectivity. Utilizing advanced 3D interconnect technology, HMC blends the best of logic and DRAM processes into a heterogeneous package. The foundation of HMC is a small logic layer that sits below vertical stacks of DRAM die connected by through-silicon-via (TSV) bonds. An energy-optimized DRAM array provides efficient access to memory bits via the logic layer, creating an intelligent memory device that’s truly optimized for performance and energy efficiencies. This elemental change in how memory is built into a system is paramount. By placing intelligent memory on the same substrate as the logic, each part of the system can function as it’s designed more efficiently than with previous technologies.

What are the measurable benefits of HMC?

HMC is a revolutionary innovation in DRAM memory architecture that delivers memory performance, power, reliability, and cost like never before. This major technology leap breaks through the memory wall, unlocking previously unthinkable processing power and ushering in a new generation of computing.

  • Increased Bandwidth − A single HMC unit can provide up to 15 times the bandwidth of a DDR3-1333 module.
  • Reduced Latency – With vastly more responders built into HMC, we expect lower queue delays and higher bank availability, which will provide a substantial system latency reduction—a key advantage in networking system design.
  • Power Efficiency − HMC’s revolutionary architecture enables greater power efficiency and energy savings, utilizing up to 70% less energy per bit than DDR3-1333 DRAM technologies.
  • Smaller Physical Footprint − HMC’s stacked architecture uses nearly 90% less physical space than today’s RDIMMs.
  • Pliable to Multiple Platforms − Logic layer flexibility enables HMC to be tailored to multiple platforms and applications.
  • Ultra Reliability HMC delivers greater resilience and field reparability with a new paradigm of system-level, advanced reliability, availability, and serviceability (RAS) features that include embedded error-checking and correction capabilities.
  • Abstracted Memory − Designers can leverage HMC’s revolutionary features and performance without having to interface with complex memory parameters. HMC manages error correction, resiliency, refresh, and other parameters exacerbated by memory process variation.
What does the implementation of HMC look like?

HMC is tightly coupled with CPUs, GPUs, and ASICS in direct point-to-point configurations where HMC performance is essential to system performance. The result is low pin counts with easy board routing in straightforward designs. In systems that require higher density, HMC supports chaining and half-width link configurations to keep the host pin counts down and the designs simple.

What are challenges of HMC implementation?

As with any leading technology, some of the “copy and paste” aspects of using older designs are lost.  However, with Micron’s support documents and a fast-growing ecosystem, you’ll be up-to-speed in no time.

What industries/segments do you anticipate will be affected the most?

Any applications where high performance and energy efficiency are critical will be dramatically affected by this technology. For example, the challenge for network systems to maintain line speed performance provides an excellent opportunity for HMC. System developers recognize that a memory bottleneck exists for system development beyond 100Gb and are actively looking for high-performance memory applications for data packet processing and data packet buffering or storage.

The high-performance computing segment is also hitting the memory wall. While processor roadmaps attempt to keep pace through core and thread doubling, core and thread count has not been matched with adequate memory performance. The second major challenge for high-performance computing is energy consumption. Higher-performance processing and exponential bit growth requirements are pushing data centers beyond practical limits for managing power and total cost of ownership. A more energy-efficient solution is desperately needed.
What is the HMCC and what are its goals?

The Hybrid Memory Cube Consortium (HMCC) is a working group made up of industry leaders who build, design in, or enable HMC technology. The goal of the HMCC is to define industry-adoptable HMC interfaces and to facilitate the integration of HMC into a wide variety of applications that enable developers, manufacturers, and enablers to leverage this revolutionary technology.

What does the HMCC specification cover?

The specification includes two PHY definitions and a common protocol. The short-reach (SR) PHY is designed for applications needing channel lengths up to 8 inches, and the ultra short-reach (USR) PHY is intended for applications requiring very short and power-efficient channels with lengths from 1 to 2 inches.

Where can the HMCC specification be accessed?

The HMCC specification is publically available on hybridmemorycube.org.

What Micron parts are available?

Our 2GB HMC device composed of a stack of four 4Gb DRAM die is available. HMC is designed using the HMCC’s short-reach (SR) PHY definition and is available in a 31mm x 31mm package offering four links with full 160 GB/s bandwidth.

When is Micron planning for HMC volume production?


How do I access a data sheet or technical information for Micron’s HMC parts?

HMC technical documents—including the datasheet—are only available under a non-disclosure agreement (NDA).  Please work with your sales representative for access.

Knights Landing(8)
What is Micron announcing regarding Intel’s Knights Landing next-generation CPU architecture?

The high-performance, on-package memory found in Knights Landing leverages the fundamental DRAM and stacking technologies also found in Micron’s HMC products.

Is this high-performance, on-package memory the same as HMC?

While leveraging the same fundamental technology benefits of HMC, this high-performance on-package memory has been optimized for integration into Knights Landing platforms.

How have Intel and Micron collaborated to bring this solution to fruition?

Micron and Intel have been collaborating on methods to break down the memory wall for years. The teams demonstrated early success at IDF 2011 where Micron’s HMC Gen1 device and an Intel memory interface targeted at many-core CPUs provided a sneak peek at the future of memory.

Are there plans to use this high-performance, on-package memory on other (future) Intel platforms?

Both Micron and Intel believe that high-performance, on-package memory will play a significant role in multi-core CPU architectures now and in the future.

Will this high-performance, on-package memory be available to other customers?

No, this memory solution has been developed specifically for Intel’s Knights Landing.

Will Intel standardize high-performance, on-package memory?

This memory solution was developed with the intent of being integrated into the Knights Landing platform; there is no plan for standardization at this time.

What is the value that high-performance, on-package memory brings to Knights Landing?

Just like HMC, high-performance, on-package memory provides unprecedented levels of memory bandwidth with a fraction of the energy and footprint of existing memory technologies along with the RAS capabilities required by HPC systems.

How does high-performance, on-package memory differ from what is being developed within the HMC Consortium?

The HMC Consortium (HMCC) is devoted to developing and driving open-standard interface and protocol platforms.

Multichip Packages(14)
Can I use a discrete package with the OMAP35x?
The PoP versions of the OMAP35x (package designations, CBC and CBB) are specifically designed to take advantage of the PoP interface for the NAND and Mobile LPDDR signals through the top of the OMAP package. However, you can route the NAND and Mobile LPDDR signals out of the bottom of the OMAP to a discrete package. The nonPoP OMAP35x package (package designation CUS) is specifically designed to use discrete memory packages.
Do I use only Mobile LPDDR with the OMAP35x, or can I use a standard SDR/DDR/DDR2/DDR3 part?
The OMAP35x is only compatible with Mobile LPDRAM. Standard SDR/DDR/DDR2/DDR3 is not supported.
Do you have any reliability data on the PoP?
Yes. We do have reliability data on the PoP. Contact Micron for more information.
For a PoP/MCP, does the qualification testing at the factory differ from testing on the discrete components?
No. the PoP/MCP parts undergo the same qualification testing as the discrete components.
How do I know the Micron part number for the part on the Beagle Board?
The Beagle Board uses our NAND + Mobile LPDDR PoP combination parts, and the densities vary depending on which version of the Beagle Board you have. Type the second 5-digit alphanumeric code on the physical part into our FBGA Decoder, which will provide you with the corresponding Micron part number.
I am using the Logic Zoom OMAP35x kit. What is the Micron part number for the part used on this platform?
The Logic Zoom OMAP35x kit uses our NAND + Mobile LPDDR PoP combination parts, and the densities vary depending on which Logic Zoom OMAP35x kit that you have. Type the second 5-digit alphanumeric code on the physical part into our FBGA Decoder, which will provide you with the corresponding Micron part number.
I’ve heard that opting for a PoP/MCP solution is more expensive than using discretes, so why should I use it?
From a system-solution perspective, because the PoP mates directly onto the processor, it eliminates the need to have traces routed on the PCB. This saves costs for the customer, as well as provides better signal integrity.
Our contract manufacturer has little experience with PoP. Why should we try something new?
The market is driving the requirement for the smaller PoP form factor, and several contract manufacturers have already enabled this technology. PoP can help save in routing costs and improve signal integrity. Given those cost and performance advantages, Micron recommends that you work very closely with your CM to ensure a good transition to this technology. Micron worked closely with Texas Instruments (TI) on the technical notes PCB Design Guidelines Part I and PCB Assembly Guidelines Part II. These can also help provide guidelines to help you work with your CM for the best success on your conversion to PoP.
We designed in discrete parts, but now we are using PoP parts. They appear to be limited in what speeds we can achieve. What is the problem?
When moving from testing with discrete parts to PoP, care should be taken that no stubs are left from the design containing the discrete components. If needed, a 0 Ohm resistor could isolate the memory from the traces used for the discrete part.
What are your PoP/MCP offerings for x8 NAND and/or x16 Mobile LPDDR?
Our standard offerings are x16 NAND and x32 Mobile LPDDR. We also have x8 NAND and x16 Mobile LPDDR. For the most current information, contact your local Micron support.
What is an MCP? What is a PoP? What is the difference between the two devices?

MCP is multichip package that contains multiple die and can be used by any controller. PoP is a form of an MCP made specifically to stack on top of a processor that has pads on the top side that mate to the ballout of the PoP. Because the PoP package stacks right on top of the processor, it eliminates the need to have traces routed on the PCB and provides better signal integrity. A variety of PoP packages are designed for various processors. PoP and MCP devices give designers the ability to take advantage of z space and to provide the flexibility to offer different logic in one package (for example, NAND + Mobile LPDDR or e.MMC™ + NAND + Mobile LPDDR). We have a wide selection of offerings to meet our customer’s needs.

What is the maximum amount of memory that Micron can support on the OMAP35x processors?
Micron works closely with Texas Instruments (TI) to validate and optimize our parts for the OMAP35x processors. As we work with the OMAP35x team, the list of validated memory devices expands frequently. For the most current information, contact your local Micron support, or send an e-mail to mcpsupport@micron.com.
What parts have been validated for TI OMAP processors?
Micron works closely with Texas Instruments (TI) to validate and optimize our parts for the OMAP35x processors. As we work with the OMAP35x team, the list of validated memory devices expands frequently. For the most current information, contact your local Micron support, or send an e-mail to mcpsupport@micron.com.
What PoP/MCP parts have been validated with the OMAP35x?
Micron works closely with Texas Instruments (TI) to validate and optimize our parts for the OMAP35x processors. As we work with the OMAP35x team, the list of validated memory devices expands frequently. For the most current information, contact your local Micron support, or contact Micron Product Technical Support. Be sure to select MCP for the quickest response time.
Solid State Storage(1)
Client SSD(1)
Can I buy a Micron SSD for personal use?

We sell SSDs (and memory) direct to the consumer through our Crucial brand. Crucial SSDs offer the same great quality, reliability, and performance of Micron SSDs, but are packaged for consumer sales. You can buy one today at crucial.com/ssd.

Advanced Computing Solutions(4)
Is Pico Computing now part of Micron?
In 2015 Micron Technology acquired Pico Computing, an industry leader in FPGA solutions. Now known as Micron Advanced Computing Solutions (ACS), our modular, highly scalable FPGA-based HPC and embedded systems comprise the industry’s leading technology for high-performance computing.
Does Micron favor Xilinx® or Altera® (Intel®) FPGAs?
Micron does not favor one or the other. Our ACS modules are designed around the latest-generation FPGA components from either Xilinx or Intel, depending on design goals and specific customer requirements.
Getting Started(3)
How do I get started with your system?
All of our ACS hardware comes with an installer file. Simply print out the Getting Started file and follow the directions. The C++ API source files that are included contain a PicoDrv, which represents an FPGA.
How do I interface with a host processor?
You interface like you would in any other system that utilizes PCIe® add-in cards.
How do I use more than one module?
Our PicoFramework provides access to all basic FPGA functionality regardless of the number of modules. The software API includes a source file called PicoDrv, which creates a PicoDrv object for each FPGA module in a system, making FPGA module communication simple.
Programming FPGAs(3)
How do I upload my bitfile to an FPGA in your system?
Our PicoFramework provides access to all of the basic FPGA functionality in your system. When you build a configuration file for an FPGA, the PicoFramework software will be the top level, and your module will be instantiated inside the framework. You create a PicoDrv object for each FPGA in the system.
What is the loading mechanism for backplane-mounted modules?
Programming an ACS module is accomplished via the PCIe® bus. Our EX-700 and EX-750 backplanes include a Spartan-6 FPGA that is used to load the ACS FPGA modules utilizing API calls. We also support and provide examples of DMA transfers through PCIe.
If I have a size-constrained application, do I need to use a backplane?
Our EX-700 and EX-750 backplanes are not technically required when using Micron’s ACS FPGA modules. Our modules can run in stand-alone with the bitfile programmed into the configuration flash, which then loads the FPGA.
Design Flows(6)
Do I need to migrate my entire application to a Micron ACS FPGA module to realize the performance advantage?
No. Simply move your application’s “hot spot” to the FPGA module and then execute a function call from the main application that remains on the traditional CPU-based system.
How do I recompile my legacy serial code to run on Micron’s ACS products?
Existing code written for serial processors should not be recompiled to run on highly parallel FPGA architectures because the many parallel benefits of the FPGA will not be realized. In fact, FPGAs are clocked much slower than CPUs (a significant power consumption benefit), so serial code would run even slower. Existing code should be analyzed to discern where the parallel nature of FPGAs offers the largest benefits, and only that part of the code should be rewritten to take advantage of the parallel nature of FPGAs. This way, the biggest benefit can be realized with the smallest effort.
Which tools do I need to use to utilize Micron’s ACS FPGA modules?
The PicoFramework doesn’t constrain your selection of FPGA design tools. Use whichever tools you are currently using for your FPGA development and whichever tools you are most comfortable with.
Does Micron ACS support OpenCL?
Yes. Both Intel’s OpenCL™ and Xilinx’s SDAccel can be used with PicoFramework. Use whichever tools you are currently using for your FPGA development and whichever tools you are most comfortable with.
Do I need to start from scratch?
No. To start your own project, simply find the sample that best matches your communication model and ACS module/board, and copy it to your work directory. The copy function will provide all source files for the PicoFramework; you will just need to add your own code.
What simulators does Micron’s ACS support?
We currently support both the Xilinx® ISim and the Altera® ModelSim (Mentor’s simulator) simulators.