DRAM Design Analysis Kits
Need to run more than just simulation models? Here are some great tools for you to use for analyzing your designs.
Micron has assisted leading EDA software vendors to offer design analysis kits that combine models for memory components, motherboards, and controllers that greatly enhance both signal integrity and timing analysis capabilities.
The tools and models available in the kits are intended to help accelerate a product's time to market, increase design efficiency, and make the design process considerably easier. They are preconfigured and ready to use. Memory channel design analysis kits, with their practical software enhancements, enable you to perform SI and timing analysis simulations more efficiently than with standard simulation models.
The DDR2 Design-In IP Portfolio Kit from Cadence Design Systems, Inc.
The DDR2 Design-In IP Portfolio, guides a designer step-by-step through the design process. It combines memory models from Micron with Altera Corporation's Stratix II memory reference design board. Scroll down for more information.
The tools in this kit include:
- Predefined topologies for UDIMM and on-board memory interfaces
- Scripting to aid in slew rate derating for complete timing analysis
- Bus analysis for termination schemes
- Detailed design methodology including verification of I/O models, stack-up design, topology design, prelayout timing budget analysis, routing constraint implementation, and postlayout timing and SI verification
Download the DDR2 Design-In IP Portfolio Kit.
DDR2 SODIMM kit available from Signal Integrity Software, Inc., (SiSoft)
- You will be redirected to the Cadence Silicon Design-In IP Portfolios Web page.
- Scroll down the page to find the "DDR2 Design-in IP" link.
The kit contains parameterized topologies for each one slot and two slot SoDIMM configuration utilizing JEDEC raw cards A, B, C and D, IBIS and timing models for DDR2 SDRAM memory devices from Micron, and IBIS and timing models for a generic memory controller. Scroll down for more information.
The design of a robust memory channel can be difficult and can involve tedious analysis work. Even with the availability of simulation models, the inherent complexities of simulation and optimization slow the process considerably. This increases the time to market by extending the duration of a project's design cycle. Lost time often means lost customers and lost ground in the market space.
Signal Integrity Software, Inc., (SiSoft) has a kit available for DDR2 SODIMMs. The tools in this memory channel design analysis kit include:
- A complete pre-layout analysis environment
- Full schematic sets
- Comprehensive timing analysis, including slew rate derating
- Timing analysis from DQS, DQ, or CLK to address, command, or control
- Easily configured on-die termination analysis
- The memory component models, DIMM models, and timing analysis models for Micron memory modules are preconfigured using a complete simulation database.
Download the DDR2 SODIMMs Kit.