Orderable parts



  • Chipset Validation
  • Density
  • FBGA Code
  • Media
  • Op. Temp.
    -40C to +85C
  • Part Status
  • PLP
  • PLP Start Date
  • Type
    Multi I/O
  • Width

Data Sheets

MT25Q sector rollover errata for FAST READ operations starting from addresses 0xFFF9-0xFFFF

FAST READ operations starting from an address within the last 7 bytes (0xFFF9-0xFFFF) of a sector “N” and sequentially reading across more than one subsequent sector boundary (e.g. sectors “N+1”, “N+2”…) is not working properly
  • File Type: PDF
  • Updated: 2/2/2015

DSV - MT25Q 1Gb, 1.8V, Multiple I/O Serial Flash Memory

Data Sheet Variance on Icc specifications.
  • File Type: PDF
  • Updated: 6/9/2014

MT25Q 1Gb, 1.8V, Multiple I/O Serial Flash Memory

The MT25Q is a high-performance multiple input/output, 1Gb, 1.8V, SPI Flash memory device; MT25QU01GBBA
  • File Type: PDF
  • Updated: 8/6/2014


China RoHS Certificate

Part-specific certification as required by China's Management Methods for Controlling Pollution by Electronic Information Products.
  • File Type: (PDF)
  • Updated: 01/2019

RoHS Certificate of Compliance

Part-specific certification of how this product meets the requirements of the current DIRECTIVE 2011/65/EU and 2015/863/EU, a.k.a. Restriction of Hazardous Substances (RoHS) Directive (Recast) without exemptions.
  • File Type: (PDF)
  • Updated: 01/2019

Simulation Models


Verilog model: MT25QU01GBBA8E
  • File Type: GZ
  • Updated: 6/29/2015


Verilog model, Standard model, MT25QU01GBBB8Epp-0
  • File Type: GZ
  • Updated: 3/13/2017

IBIS_MT25QU01GBBAxx12-xxTT v2.1

  • File Type: ZIP
  • Updated: 9/3/2015


PP= 12, SF, W9. TT= IT, AT, AUT.
  • File Type: ZIP
  • Updated: 9/25/2017

Technical Notes

TN-25-05: N25Q and MT25Q Serial Flash Stacked Devices

This technical note describes the features of stacked devices for N25Q and MT25Q. These devices are memory with two or more dies in the same package.
  • File Type: PDF
  • Updated: 5/8/2017

TN-25-07: Tuning Data Pattern for MT25Q and MT25T Devices

This technical note describes the Tuning Data Pattern (TDP). TDP provides applications with a set of data patterns which can be used to adjust the data latching point at the host end when the clock frequency is set higher than 133 MHz in STR mode and higher than 66 MHz in double transfer rate (DTR) mode.
  • File Type: PDF
  • Updated: 4/23/2015

Customer Service Notes

Micron Component and Module Packaging

Explanation of Micron packaging labels and procedures.
  • File Type: PDF
  • Updated: 10/12/2018

ESD Precautions for Die/Wafer Handling and Assembly

Describes the benefits of controlling ESD in the workplace, including higher yields and improved quality and reliability, resulting in reduced manufacturing costs.
  • File Type: PDF
  • Updated: 8/5/2010