A Revolution in Memory
Multi-core processing is bringing incredible advances to supercomputing and advanced networking systems— advances that require a new level of memory efficiency and performance. In October, 2011, we joined a group of industry leaders to develop an entirely new memory architecture—the Hybrid Memory Cube (HMC)—which maximizes the full potential of these high-performance systems. HMC represents a fundamental change in how memory is used in the system. This elemental change is paramount. By tightly coupling intelligent memory with CPUs, GPUs, and ASICs, systems can enable dramatic improvements in efficiency and power optimization.
How HMC Works
At the core of the HMC is a small, high-speed logic layer that sits below vertical stacks of DRAM die that are connected using through-silicon-via (TSV) interconnects. The DRAM has been designed solely to handle data, with the logic layer handling all DRAM control within the HMC. System designers have the option of using the HMC as either "near memory," mounted directly adjacent to the processors for best performance, or in a scalable module form factor as "far memory," for optimized power efficiency.
The HMC Consortium (HMCC)
is a working group made up of industry leaders who build, design in, or
enable HMC technology. The HMCC is led by nine developers—Altera, ARM,
IBM, SK Hynix, Micron, Open-Silicon, Samsung, Semtech and Xilinx—and drives
broad agreement of HMC standards with the help of more than 120
consortium adopters. The HMC 1.0 Specification
was finalized and released to the public on April 2, 2013 and provides a short-reach (SR) link definition designed for applications
needing channel lengths up to 8 inches. HMC targets networking and high performance computing segments providing high-bandwidth memory. In 2014 the HMCC released the HMC 2.0 Specification. HMC 2.0 provides a performance improvement over the HMC 1.0, increasing the link speed from 15Gbps to 30Gbps and aligns very closely the CEI 28G-VSR industry specification.
Today, the HMCC continues to drive industry adoption of this revolutionary memory with the development of a third generation specification
designed to increase both short-reach and ultra short-reach
performance. This next specification is targeted for completion and
release in 2018.
- Micron & Altera's HMC/Stratix V Interoperability Team
Named 2014 Design Team of the Year by EE Times and EDN
Hybrid Memory Cube Named 2013 Product of the Year
HMC has been recognized by industry leaders and influencers as the long-awaited answer to the growing gap between the performance improvement rate of DRAM versus processor data consumption rate—a dilemma known as the “memory wall.”
Want to Know More?
Learn more about our Short-Reach HMC, including benefits and FAQs, that are available to take your design to the next level.