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Data Sheet Uploaded 09/2014

Features

Features

PC100- and PC133-compliant

Fully synchronous; all signals registered on positive edge of system clock

Internal, pipelined operation; column address can be changed every clock cycle

Internal banks for hiding row access/precharge

Programmable burst lengths (BL): 1, 2, 4, 8, or full page

Auto precharge, includes concurrent auto precharge and auto refresh modes

Self refresh modes: Standard and low power
(not available on AT devices)

Auto Refresh

64ms, 4096-cycle refresh (commercial and
industrial)

16ms, 4096-cycle refresh (automotive)

LVTTL-compatible inputs and outputs

Single 3.3V ±0.3V power supply

Options Marking

Configurations

 

32 Meg x 4 (8 Meg x 4 x 4 banks)1

32M4

16 Meg x 8 (4 Meg x 8 x 4 banks)

16M8

8 Meg x 16 (2 Meg x 16 x 4 banks)

8M16

Write recovery (tWR)

 

tWR = 2 CLK

A2

Plastic package – OCPL2

 

54-pin TSOP II (400 mil)

TG

54-pin TSOP II (400 mil) Pb-free

P

60-ball TFBGA (8mm x 16mm)

FB1

60-ball TFBGA (8mm x 16mm) Pb-free

BB1

54-ball VFBGA (x16 only) (8mm x 8mm)

F4

54-ball VFBGA (x16 only) (8mm x 8mm) Pb-free

B4

Timing – cycle time

 

7.5ns @ CL = 3 (PC133)

-753

7.5ns @ CL = 2 (PC133)

-7E

6.0ns @ CL = 3 (x16 only)

-6A

Self refresh

Standard

None

Low power

L3

Revision

:G/:L

Operating temperature range

 

Commercial (0˚C to +70˚C)

None

Industrial (–40˚C to +85˚C)

IT

Automotive (–40˚C to +105˚C)

AT1

Notes

  1. Contact Micron for availability.

  2. Off-center parting line.

  3. Only available on Revision G.

Table 1. Key Timing Parameters

CL = CAS (READ) latency

Speed Grade Clock
Frequency (MHz)
Target tRCD-tRP-CL tRCD (ns) tRP (ns) CL (ns)
-6A 167 3-3-3 18 18 18
-75 133 3-3-3 20 20 20
-7E 133 2-2-2 15 15 15
Table 2. Address Table
Parameter 32 Meg x 4 16 Meg x 8 8 Meg x 16
Configuration 8 Meg x 4 x 4 banks 4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks
Refresh count 4K 4K 4K
Row addressing 4K A[11:0] 4K A[11:0] 4K A[11:0]
Bank addressing 4 BA[1:0] 4 BA[1:0] 4 BA[1:0]
Column addressing 2K A[9:0], A11 1K A[9:0] 512 A[8:0]
Table 3. 128Mb SDR Part Numbering

Part Numbers Architecture
MT48LC32M4A2TG 32 Meg x 4
MT48LC32M4A2P 32 Meg x 4
MT48LC16M8A2TG 16 Meg x 8
MT48LC16M8A2P 16 Meg x 8
MT48LC16M8A2FB 16 Meg x 8
MT48LC16M8A2BB 16 Meg x 8
MT48LC8M16A2TG 8 Meg x 16
MT48LC8M16A2P 8 Meg x 16
MT48LC8M16A2B4 8 Meg x 16
MT48LC8M16A2F4 16 Meg x 16

Note

  1. FBGA Device Decoder: www.micron.com/decoder

Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

General Description

General Description

The 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 33,554,432-bit banks is organized as 4096 rows by 2048 columns by 4 bits. Each of the x8’s 33,554,432-bit banks is organized as 4096 rows by 1024 columns by 8 bits. Each of the x16’s 33,554,432-bit banks is organized as 4096 rows by 512 columns by 16 bits.

Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the bank; A[11:0] select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.

The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence.

The 128Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the PRECHARGE cycles and provide seamless, high-speed, random-access operation.

The 128Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible.

The devices offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access.

Automotive Temperature

The automotive temperature (AT) option adheres to the following specifications:


  • 16ms refresh rate
  • Self refresh not supported
  • Ambient and case temperature cannot be less than –40°C or greater than +105°C

Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

Functional Block Diagrams

Functional Block Diagrams

Figure 1. 32 Meg x 4 Functional Block Diagram


Figure 2. 16 Meg x 8 Functional Block Diagram


Figure 3. 8 Meg x 16 Functional Block Diagram


Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.