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Data Sheet Uploaded 09/2015

Features

Features

High performance

100ns initial access for Easy BGA

110ns initial access for TSOP

25ns 16-word asychronous page read mode

52 MHz (Easy BGA) with zero WAIT states and 17ns clock-to-data output synchronous burst read mode

4-, 8-, 16-, and continuous word options for burst mode

Buffered enhanced factory programming (BEFP) at 2 MB/s (TYP) using a 512-word buffer

1.8V buffered programming at 1.14 MB/s (TYP) using a 512-word buffer

Architecture

MLC: highest density at lowest cost

Asymmetrically blocked architecture

Four 32KB parameter blocks: top or bottom configuration

128KB main blocks

Blank check to verify an erased block

Voltage and power

VCC (core) voltage: 1.7V to 2.0V

VCCQ (I/O) voltage: 1.7V to 3.6V

Standy current: 65µA (TYP) for 256Mb

52 MHz continuous synchronous read current: 21mA (TYP), 24mA (MAX)

Security

One-time programmable register: 64 OTP bits, programmed with unique information from Micron; 2112 OTP bits available for customer programming

Absolute write protection: VPP = VSS

Power-transition erase/program lockout

Individual zero-latency block locking

Individual block lock-down

Password access

Software

25μs (TYP) program suspend

25μs (TYP) erase suspend

Flash Data Integrator optimized

Basic command set and extended function Interface (EFI) command set compatible

Common flash interface

Density and Packaging

56-lead TSOP package (256Mb only)

64-ball Easy BGA package (256Mb, 512Mb)

QUAD+ and SCSP packages (256Mb, 512Mb)

16-bit wide data bus

Quality and reliabilty

JESD47 compliant

Operating temperature: –40°C to +85°C

Minimum 100,000 ERASE cycles per block

65nm process technology

Discrete and MCP Part Numbering Information

Devices are shipped from the factory with memory content bits erased to 1. For available options, such as packages or for further information, contact your Micron sales representative. Part numbers can be verified at www.micron.com . Feature and specification comparison by device type is available at www.micron.com/products . Contact the factory for devices not found.

Note: Not all part numbers listed here are available for ordering.

Table 1. Discrete Part Number Information

Part Number Category Category Details
Package JS = 56-lead TSOP, lead free
PC = 64-ball Easy BGA, lead-free
RC = 64-ball Easy BGA, leaded
Product Line 28F = Micron Flash memory
Density 256 = 256Mb
Product Family P30 (VCC = 1.7 to 2.0V; VCCQ = 1.7 to 3.6V)
Parameter Location B/T = Bottom/Top parameter
Lithography F = 65nm
Features *

Note

  1. The last digit is assigned randomly to cover packaging media, features, or other specific configuration information. Sample part number: JS28F256P30BF*

Table 2. MCP Part Number Information

Part Number Category Category Details
Package RD = Micron MCP, leaded
PF = Micron MCP, lead-free
RC = 64-ball Easy BGA, leaded
PC = 64-ball Easy BGA, lead-free
Product Line 48F = Micron Flash memory only
Density 0 = No die
4 = 256Mb
Product Family P = Micron Flash memory (P30)
0 = No die
IO Voltage and Chip Configuration Z = Individual Chip Enables
V = Virtual Chip Enables
VCC = 1.7 to 2.0V; VCCQ = 1.7 to 3.6V
Parameter Location B/T = Bottom/Top parameter
Ballout Q = QUAD+
0 = Discrete
Lithography E = 65nm
Features *

Note

  1. The last digit is assigned randomly to cover packaging media, features, or other specific configuration information. Sample part number: RC48F4400P0VB0E*

Table 3. Discrete and MCP Part Combinations

Package Density Packing Media Boot Configuration 1 Part Number
JS 256Mb Tray B JS28F256P30BFE
Tape and Reel JS28F256P30BFF
Tray T JS28F256P30TFE
PC 256Mb Tray B PC28F256P30BFE
Tape and Reel PC28F256P30BFF
Tray T PC28F256P30TFE
512Mb
(256Mb/256Mb)
Tray B/T PC48F4400P0VB0EE
Tape and Reel PC48F4400P0VB0EF
PF 256Mb Tray B PF48F4000P0ZBQEF
Tray T PF48F4000P0ZTQEJ
512Mb
(256Mb/256Mb)
Tray B/T PF48F4400P0VBQEF
Tape and Reel PF48F4400P0VBQEK
RC 256Mb Tray B RC28F256P30BFE
Tray T RC28F256P30TFE
Tape and Reel RC28F256P30TFF
512Mb
(256Mb/256Mb)
Tray B/T RC48F4400P0VB0EJ
RD 512Mb
(256Mb/256Mb)
Tray B/T RD48F4400P0VBQEJ

Note

  1. Bottom Boot/Top Boot = B/T

Table 4. OTP Feature Part Combinations

Package Density Packing Media Boot Configuration 1 Part Number
JS
PC 256Mb Tape and Reel B PC28F256P30BFR
PF
RC
RD

Notes

  1. This data sheet covers only standard parts. For OTP parts, contact your local Micron representative.

  2. Bottom Boot/Top Boot = B/T

Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

General Description

General Description

The Micron Parallel NOR Flash memory is the latest generation of Flash memory devices. Benefits include more density in less space, high-speed interface device, and support for code and data storage. Features include high-performance synchronous-burst read mode, fast asynchronous access times, low power, flexible security options, and three industry-standard package choices. The product family is manufactured using Micron 65nm process technology.

The NOR Flash device provides high performance at low voltage on a 16-bit data bus. Individually erasable memory blocks are sized for optimum code and data storage.

Upon initial power up or return from reset, the device defaults to asynchronous page-mode read. Configuring the read configuration register enables synchronous burst-mode reads. In synchronous burst mode, output data is synchronized with a user-supplied clock signal. A WAIT signal provides easy CPU-to-flash memory synchronization.

In addition to the enhanced architecture and interface, the device incorporates technology that enables fast factory PROGRAM and ERASE operations. Designed for low-voltage systems, the devIce supports READ operations with VCC at the low voltages, and ERASE and PROGRAM operations with VPP at the low voltages or VPPH. Buffered enhanced factory programming (BEFP) provides the fastest Flash array programming performance with VPP at VPPH, which increases factory throughput. With VPP at low voltages, VCC and VPP can be tied together for a simple, ultra low-power design. In addition to voltage flexibility, a dedicated VPP connection provides complete data protection when VPP ≤ VPPLK.

A command user interface is the interface between the system processor and all internal operations of the device. The device automatically executes the algorithms and timings necessary for block erase and program. A status register indicates ERASE or PROGRAM completion and any errors that may have occurred.

An industry-standard command sequence invokes program and erase automation. Each ERASE operation erases one block. The erase suspend feature enables system software to pause an ERASE cycle to read or program data in another block. Program suspend enables system software to pause programming to read other locations. Data is programmed in word increments (16 bits).

The protection register enables unique device identification that can be used to increase system security. The individual block lock feature provides zero-latency block locking and unlocking. The device includes enhanced protection via password access; this new feature supports write and/or read access protection of user-defined blocks. In addition, the device also provides the full-device OTP security feature.

Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

Virtual Chip Enable Description

Virtual Chip Enable Description

The 512Mb device employs a virtual chip enable feature, which combines two 256Mb die with a common chip enable, F1-CE# for QUAD+ packages, or CE# for Easy BGA packages. The maximum address bit is then used to select between the die pair with F1-CE#/CE# asserted, depending upon the package option used. When F1-CE#/CE# is asserted and the maximum address bit is LOW, the lower parameter die is selected; when F1-CE#/CE# is asserted and the maximum address bit is HIGH, the upper parameter die is selected.

Table 1. Virtual Chip Enable Truth Table for 512Mb (QUAD+ Package)
Die Selected F1-CE# A24
Lower Param Die L L
Upper Param Die L H
Table 2. Virtual Chip Enable Truth Table for 512Mb (Easy BGA Packages)
Die Selected CE# A25
Lower Param Die L L
Upper Param Die L H
Figure 1. 512Mb Easy BGA Block Diagram


Figure 2. 512Mb QUAD+ Block Diagram


Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.