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Data Sheet Uploaded 07/2011

Features

Features


  • VDD = 2.5V ±0.2V, VDDQ = 2.5V ±0.2V

    VDD = 2.6V ±0.1V, VDDQ = 2.6V ±0.1V (DDR400)1

  • Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture (x16 has two – one per byte)

  • Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle

  • Differential clock inputs (CK and CK#)

  • Commands entered on each positive CK edge

  • DQS edge-aligned with data for READs; center- aligned with data for WRITEs

  • DLL to align DQ and DQS transitions with CK

  • Four internal banks for concurrent operation

  • Data mask (DM) for masking write data 
(x16 has two – one per byte)

  • Programmable burst lengths: 2, 4, or 8

  • Auto refresh

    64ms, 8192-cycle

  • Longer-lead TSOP for improved reliability (OCPL)

  • 2.5V I/O (SSTL_2 compatible)

  • Concurrent auto precharge option is supported

  • tRAS lockout supported (tRAP = tRCD)

Options Marking

Configuration

 

128 Meg x 4 (32 Meg x 4 x 4 banks)

128M4

64 Meg x 8 (16 Meg x 8 x 4 banks)

64M8

32 Meg x 16 (8 Meg x 16 x 4 banks)

32M16

Plastic package

 

66-pin TSOP

TG

66-pin TSOP (Pb-free)

P

60-ball FBGA (10mm x 12.5mm)

FN2

60-ball FBGA (10mm x 12.5mm) (Pb-free)

BN2

60-ball FBGA (8mm x 12.5mm)

CV3

60-ball FBGA (8mm x 12.5mm) (Pb-free)

CY3

Timing – cycle time

 

5ns @ CL = 3 (DDR400)

-5B

6ns @ CL = 2.5 (DDR333) (FBGA only)

-62

6ns @ CL = 2.5 (DDR333) (TSOP only)

-6T2

Self refresh

 

Standard

None

Low-power self refresh

L

Temperature rating

 

Commercial (0°C to +70°C)

None

Industrial (–40°C to +85°C)

IT

Revision

 

x4, x8, x16

:F

x4, x8, x16

:J

Notes

  1. DDR400 devices operating at < DDR333
conditions can use VDD/VDDQ = 2.5V +0.2V.

  2. Available only on Revision F.

  3. Available only on Revision J.

Table 1. Key Timing Parameters

CL = CAS (READ) latency; data-out window is MIN clock rate with 50% duty cycle at CL = 2, CL = 2.5, or CL = 3

Speed
Grade Clock Rate (MHz) Data-Out Window Access
Window DQS–DQ
Skew
CL = 2 CL = 2.5 CL = 3
-5B 133 167 200 1.6ns ±0.70ns 0.40ns
-6 133 167 n/a 2.1ns ±0.70ns 0.40ns
6T 133 167 n/a 2.0ns ±0.70ns 0.45ns
-75E/-75Z 133 133 n/a 2.5ns ±0.75ns 0.50ns
-75 100 133 n/a 2.5ns ±0.75ns 0.50ns
Table 2. Addressing
Parameter 128 Meg x 4 64 Meg x 8 32 Meg x 16
Configuration 32 Meg x 4 x 4 banks 16 Meg x 8 x 4 banks 8 Meg x 16 x 4 banks
Refresh count 8K 8K 8K
Row address 8K (A0–A12) 8K (A0–A12) 8K (A0–A12)
Bank address 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)
Column address 4K (A0–A9, A11, A12) 2K (A0-A9, A11) 1K (A0–A9)
Table 3. Speed Grade Compatibility

Marking PC3200 (3-3-3) PC2700 (2.5-3-3) PC2100 (2-2-2) PC2100 (2-3-3) PC2100 (2.5-3-3) PC1600 (2-2-2)
-5B1 Yes Yes Yes Yes Yes Yes
-6 Yes Yes Yes Yes Yes
-6T Yes Yes Yes Yes Yes
-75E Yes Yes Yes Yes
-75Z Yes Yes Yes
-75 Yes Yes
  -5B -6/-6T -75E -75Z -75 -75

Note

  1. The -5B device is backward-compatible with all slower speed grades. The voltage range of 
-5B device operating at slower speed grades is VDD = VDDQ = 2.5V ± 0.2V.

Figure 1. 512Mb DDR SDRAM Part Numbers

Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

FBGA Part Number System

FBGA Part Number System

Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site:

Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

State Diagram

State Diagram

Figure 1. Simplified State Diagram

Note

  1. This diagram represents operations within a single bank only and does not capture concurrent operations in other banks.

Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.