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Data Sheet Uploaded 09/2015

Features

Features


  • 533 MHz DDR operation (1.067 Gb/s/pin data rate)

  • 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock frequency)

  • Organization

    64 Meg x 9, 32 Meg x 18, and 16 Meg x 36 I/O

    8 banks

  • Reduced cycle time (15ns at 533 MHz)

  • Nonmultiplexed addresses (address multiplexing option available)

  • SRAM-type interface

  • Programmable READ latency (RL), row cycle time, and burst sequence length

  • Balanced READ and WRITE latencies in order to optimize data bus utilization

  • Data mask for WRITE commands

  • Differential input clocks (CK, CK#)

  • Differential input data clocks (DKx, DKx#)

  • On-die DLL generates CK edge-aligned data and output data clock signals

  • Data valid signal (QVLD)

  • 32ms refresh (16K refresh for each bank; 128K refresh command must be issued in total each 32ms)

  • HSTL I/O (1.5V or 1.8V nominal)

  • 25–60Ω matched impedance outputs

  • 2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O

  • On-die termination (ODT) RTT

Options1 Marking

Clock cycle timing

 

1.875ns @ tRC = 15ns

-18

2.5ns @ tRC = 15ns

-25E

2.5ns @ tRC = 20ns

-25

3.3ns @ tRC = 20ns

-33

Configuration

64 Meg x 9

64M9

32 Meg x 18

32M18

16 Meg x 36

16M36

Operating temperature

 

Commercial (0° to +95°C)

None

Industrial (TC = –40°C to +95°C;
TA = –40°C to +85°C)

IT

Package

 

144-ball µBGA

FM

144-ball µBGA (Pb-free)

BM

144-ball FBGA

TR

144-ball FBGA (Pb-free)

SJ

Revision

:A/:B

Note

  1. Not all options listed can be combined to define an offered product. Use the part catalog search on www.micron.com for available offerings.

BGA Marking Decoder

Due to space limitations, BGA-packaged components have an abbreviated part marking that is different from the part number. Micron’s BGA Part Marking Decoder is available on Micron’s web site at .

Figure 1. Part Numbers


Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

General Description

General Description

RLDRAM® 2 is a high-speed memory device designed for high bandwidth data storage, telecommunications, networking, and cache applications, etc. The chip’s 8-bank architecture is optimized for sustainable high-speed operation.

The DDR I/O interface transfers two data words per clock cycle at the I/O balls. Output data is referenced to the free-running output data clock.

Commands, addresses, and control signals are registered at every positive edge of the differential input clock, while input data is registered at both positive and negative edges of the input data clock(s).

Read and write accesses are burst-oriented. The burst length (BL) is programmable from 2, 4, or 8 by setting the mode register.

The device is supplied with 2.5V and 1.8V for the core and 1.5V or 1.8V for the output drivers.

Bank-scheduled refresh is supported with the row address generated internally.

The µBGA 144-ball package enables ultra high-speed data transfer rates and a simple upgrade path from early generation devices.

Figure 1. Simplified State Diagram


Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

Functional Block Diagrams

Functional Block Diagrams

Figure 1. 64 Meg x 9 Functional Block Diagram



Notes

  1. Example for BL = 2; column address will be reduced with an increase in burst length.

  2. 32 = (length of burst) x 2^(number of column addresses to WRITE FIFO and READ logic).

Figure 2. 32 Meg x 18 Functional Block Diagram



Notes

  1. Example for BL = 2; column address will be reduced with an increase in burst length.

  2. 16 = (length of burst) x 2^(number of column addresses to WRITE FIFO and READ logic).

Figure 3. 16 Meg x 36 Functional Block Diagram



Notes

  1. Example for BL = 2; column address will be reduced with an increase in burst length.

  2. 8 = (length of burst) x 2^(number of column addresses to WRITE FIFO and READ logic).

Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.