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Data Sheet Uploaded 03/2010

Features

Features


  • 244-pin, very low profile mini registered dual in-line memory module

  • Fast data transfer rates: PC2-6400, PC2-5300, PC2-4200, or PC2-3200

  • 512MB (64 Meg x 72) or 1GB (128 Meg x 72)

  • Supports ECC error detection and correction

  • VDD = VDDQ = 1.8V

  • VDDSPD = 1.7–3.6V

  • JEDEC-standard 1.8V I/O (SSTL_18-compatible)

  • Differential data strobe (DQS, DQS#) option

  • 4n-bit prefetch architecture

  • Multiple internal device banks for concurrent
    operation

  • Programmable CAS latency (CL)

  • Posted CAS additive latency (AL)

  • WRITE latency = READ latency - 1 tCK

  • Programmable burst lengths: 4 or 8

  • Adjustable data-output drive strength

  • 64ms, 8192-cycle refresh

  • On-die termination (ODT)

  • Serial presence-detect (SPD) with EEPROM

  • Gold edge contacts

  • Single rank

  • Lead-free

    Figure 1. 244-Pin VLP Mini-RDIMM

    Options Marking

    Parity

    P

    Operating temperature

     

    Commercial (0°C ≤ TA ≤ 70°C)

    None

    Industrial (–40°C ≤ TA ≤ 85°C)1

    I

    Package

     

    244-pin DIMM (lead-free)

    Y

    Frequency/CL2

     

    2.5ns @ CL = 5 (DDR2-800)

    -80E

    2.5ns @ CL = 6 (DDR2-800)

    -800

    3.0ns @ CL = 5 (DDR2-667)

    -667

    3.75ns @ CL = 4 (DDR2-533)

    -53E

    5.0ns @ CL = 3 (DDR2-400)

    -40E

    Notes

    1. Contact Micron for industrial temperature module offerings.

    2. CL = CAS (READ) latency; registered mode will add one clock cycle to CL.

Table 1. Key Timing Parameters
Speed Grade Industry
Nomenclature
Data Rate (MT/s) tRCD
(ns)
tRP
(ns)
tRC
(ns)
CL = 6 CL = 5 CL = 4 CL = 3
-80E PC2-6400 800 800 533 400 12.5 12.5 55
-800 PC2-6400 800 667 533 400 15 15 55
-667 PC2-5300 667 553 400 15 15 55
-53E PC2-4200 553 400 15 15 55
-40E PC2-3200 400 400 15 15 55
Table 2. Addressing
  512MB 1GB
Refresh count 8K 8K
Row address 16K A[13:0] 16K A[13:0]
Device bank address 4 BA[1:0] 8 BA[2:0]
Device configuration 512Mb (64 Meg x 8) 1Gb (128 Meg x 8)
Column address 1K A[9:0] 1K A[9:0]
Module rank address 1 S0# 1 S0#
Table 3. Part Numbers and Timing Parameters – 512MB

Base device: MT47H64M8, 512Mb DDR2 SDRAM

Part Number Module Density Configuration Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
MT9HVF6472PK(I)Y-80E__ 512MB 64 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5
MT9HVF6472PK(I)Y-800__ 512MB 64 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 6-6-6
MT9HVF6472PK(I)Y-667__ 512MB 64 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5
MT9HVF6472PK(I)Y-53E__ 512MB 64 Meg x 72 4.3 GB/s 3.75ns/533 MT/s 4-4-4
MT9HVF6472PK(I)Y-40E__ 512MB 64 Meg x 72 3.2 GB/s 5.0ns/400 MT/s 3-3-3
Table 4. Part Numbers and Timing Parameters – 1GB

Base device: MT47H128M8, 1Gb DDR2 SDRAM

Part Number2 Module Density Configuration Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
MT9HVF12872PK(I)Y-80E__ 1GB 128 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5
MT9HVF12872PK(I)Y-800__ 1GB 128 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 6-6-6
MT9HVF12872PK(I)Y-667__ 1GB 128 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5
MT9HVF12872PK(I)Y-53E__ 1GB 128 Meg x 72 4.3 GB/s 3.75ns/533 MT/s 4-4-4
MT9HVF12872PK(I)Y-40E__ 1GB 128 Meg x 72 3.2 GB/s 5.0ns/400 MT/s 3-3-3

Notes

  1. Data sheets for the base devices can be found on Micron’s Web site.

  2. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT9HVF12872KY-40EE1.

Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

Pin Assignments

Pin Assignments

Table 1. Pin Assignments

244-Pin VLP Mini-RDIMM Front 244-Pin VLP Mini-RDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1 VREF 32 VSS 63 VDDQ 94 DQS5# 123 VSS 154 DQ28 185 A3 216 NF/RDQS5#
2 VSS 33 DQ24 64 A2 95 DQS5 124 DQ4 155 DQ29 186 A1 217 VSS
3 DQ0 34 DQ25 65 VDD 96 VSS 125 DQ5 156 VSS 187 VDD 218 DQ46
4 DQ1 35 VSS 66 VSS 97 DQ42 126 VSS 157 DM3/RDQS3 188 CK0 219 DQ47
5 VSS 36 DQS3# 67 VSS 98 DQ43 127 DM0/RDQS0 158 NF/RDQS3# 189 CK0# 220 VSS
6 DQS0# 37 DQS3 68 Par_In 99 VSS 128 NF/RDQS0# 159 VSS 190 VDD 221 DQ52
7 DQS0 38 VSS 69 VDD 100 DQ48 129 VSS 160 DQ30 191 A0 222 DQ53
8 VSS 39 DQ26 70 A10 101 DQ49 130 DQ6 161 DQ31 192 BA1 223 VSS
9 DQ2 40 DQ27 71 BA0 102 VSS 131 DQ7 162 VSS 193 VDD 224 RFU
10 DQ3 41 VSS 72 VDD 103 SA2 132 VSS 163 CB4 194 RAS# 225 RFU
11 VSS 42 CB0 73 WE# 104 NC 133 DQ12 164 CB5 195 VDDQ 226 VSS
12 DQ8 43 CB1 74 VDDQ 105 VSS 134 DQ13 165 VSS 196 S0# 227 DM6/RDQS6
13 DQ9 44 VSS 75 CAS# 106 DQS6# 135 VSS 166 DM8/RDQS8 197 VDDQ 228 NF/RDQS6#
14 VSS 45 DQS8# 76 VDDQ 107 DQS6 136 DM1/RDQS1 167 NF/RDQS8# 198 ODT0 229 VSS
15 DQS1# 46 DQS8 77 NC 108 VSS 137 NF/RDQS1# 168 VSS 199 A13 230 DQ54
16 DQS1 47 VSS 78 NC 109 DQ50 138 VSS 169 CB6 200 VDD 231 DQ55
17 VSS 48 CB2 79 VDDQ 110 DQ51 139 RFU 170 CB7 201 NC 232 VSS
18 RESET# 49 CB3 80 NC 111 VSS 140 RFU 171 VSS 202 VSS 233 DQ60
19 NC 50 VSS 81 VSS 112 DQ56 141 VSS 172 NC 203 DQ36 234 DQ61
20 VSS 51 NC 82 DQ32 113 DQ57 142 DQ14 173 VDDQ 204 DQ37 235 VSS
21 DQ10 52 VDDQ 83 DQ33 114 VSS 143 DQ15 174 NC 205 VSS 236 DM7/RDQS7
22 DQ11 53 CKE0 84 VSS 115 DQS7# 144 VSS 175 VDD 206 DM4/RDQS4 237 NF/RDQS7#
23 VSS 54 VDD 85 DQS4# 116 DQS7 145 DQ20 176 NC 207 NF/RDQS4# 238 VSS
24 DQ16 55 NF/BA21 86 DQS4 117 VSS 146 DQ21 177 NC 208 VSS 239 DQ62
25 DQ17 56 Err_Out# 87 VSS 118 DQ58 147 VSS 178 VDDQ 209 DQ38 240 DQ63
26 VSS 57 VDDQ 88 DQ34 119 DQ59 148 DM2/RDQS2 179 A12 210 DQ39 241 VSS
27 DQS2# 58 A11 89 DQ35 120 VSS 149 NF/RDQS2# 180 A9 211 VSS 242 SDA
28 DQS2 59 A7 90 VSS 121 SA0 150 VSS 181 VDD 212 DQ44 243 SCL
29 VSS 60 VDD 91 DQ40 122 SA1 151 DQ22 182 A8 213 DQ45 244 VDDSPD
30 DQ18 61 A5 92 DQ41     152 DQ23 183 A6 214 VSS    
31 DQ19 62 A4 93 VSS     153 VSS 184 VDDQ 215 DM5/RDQS5    

Note

  1. Pin 55 is NF for 512MB, BA2 for 1GB.

Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

Pin Descriptions

Pin Descriptions

The pin description table below is a comprehensive list of all possible pins for all DDR2 modules. All pins listed may not be supported on this module. See Pin Assignments for information specific to this module.

Table 1. Pin Descriptions
Symbol Type Description
Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. See the Pin Assignments Table for density-specific addressing information.
BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA define which mode register (MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command.
CKx,
CK#x
Input Clock: Differential clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#.
CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DDR2 SDRAM.
DMx Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write access. Although DM pins are input-only, DM loading is designed to match that of the DQ and DQS pins.
ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR2 SDRAM. When enabled in normal operation, ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input will be ignored if disabled via the LOAD MODE command.
Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered.
RESET# Input Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z.
S#x Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command decoder.
SAx Input Serial address inputs: Used to configure the SPD EEPROM address range on the I2C bus.
SCL Input Serial clock for SPD EEPROM: Used to synchronize communication to and from the SPD EEPROM on the I2C bus.
CBx I/O Check bits. Used for system error detection and correction.
DQx I/O Data input/output: Bidirectional data bus.
DQSx,
DQS#x
I/O Data strobe: Travels with the DQ and is used to capture DQ at the DRAM or the controller. Output with read data; input with write data for source synchronous operation. DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command.
SDA I/O Serial data: Used to transfer addresses and data into and out of the SPD EEPROM on the I2C bus.
RDQSx,
RDQS#x
Output Redundant data strobe (x8 devices only): RDQS is enabled/disabled via the LOAD MODE command to the extended mode register (EMR). When RDQS is enabled, RDQS is output with read data only and is ignored during write data. When RDQS is disabled, RDQS becomes data mask (see DMx). RDQS# is only used when RDQS is enabled and differential data strobe mode is enabled.
Err_Out# Output
(open drain)
Parity error output: Parity error found on the command and address bus.
VDD/VDDQ Supply Power supply: 1.8V ±0.1V. The component VDD and VDDQ are connected to the module VDD.
VDDSPD Supply SPD EEPROM power supply: 1.7–3.6V.
VREF Supply Reference voltage: VDD/2.
VSS Supply Ground.
NC No connect: These pins are not connected on the module.
NF No function: These pins are connected within the module, but provide no functionality.
NU Not used: These pins are not used in specific module configurations/operations.
RFU Reserved for future use.

Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.