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Data Sheet Uploaded 12/2013

Features

Features

High performance

Easy BGA package features

95ns initial access for 512Mb, 1Gb Easy BGA

100ns initial access for 2Gb Easy BGA

25ns 16-word asychronous page read mode

52 MHz (Easy BGA) with zero WAIT states and 17ns clock-to-data output synchronous burst read mode

4-, 8-, 16-, and continuous word options for burst mode

TSOP package features

105ns initial access for 512Mb, 1Gb TSOP

Both Easy BGA and TSOP package features

Buffered enhanced factory programming (BEFP) at 2 MB/s (TYP) using a 512-word buffer

3.0V buffered programming at 1.46 MB/s (TYP) using a 512-word buffer

Architecture

MLC: highest density at lowest cost

Symmetrically blocked architecture (512Mb, 1Gb, 2Gb)

Asymmetrically blocked architecture (512Mb, 1Gb); four 32KB parameter blocks: top or bottom configuration

128KB main blocks

Blank check to verify an erased block

Voltage and power

VCC (core) voltage: 2.3–3.6V

VCCQ (I/O) voltage: 2.3–3.6V

Standy current: 70µA (TYP) for 512Mb; 75µA (TYP) for 1Gb

52 MHz continuous synchronous read current: 21mA (TYP), 24mA (MAX)

Security

One-time programmable register: 64 OTP bits, programmed with unique information from Micron; 2112 OTP bits available for customer programming

Absolute write protection: VPP = VSS

Power-transition erase/program lockout

Individual zero-latency block locking

Individual block lock-down

Password access

Software

25μs (TYP) program suspend

30μs (TYP) erase suspend

Flash Data Integrator optimized

Basic command set and extended function Interface (EFI) command set compatible

Common flash interface

Density and Packaging

56-lead TSOP package (512Mb, 1Gb)

64-ball Easy BGA package (512Mb, 1Gb, 2Gb)

16-bit wide data bus

Quality and reliabilty

JESD47 compliant

Operating temperature: –40°C to +85°C

Minimum 100,000 ERASE cycles per block

65nm process technology

Discrete and MCP Part Numbering Information

Devices are shipped from the factory with memory content bits erased to 1. For available options, such as packages or for further information, contact your Micron sales representative. Part numbers can be verified at www.micron.com . Feature and specification comparison by device type is available at www.micron.com/products . Contact the factory for devices not found.

Table 1. Discrete Part Number Information

Part Number Category Category Details
Package JS = 56-lead TSOP, lead free
PC = 64-ball Easy BGA, lead-free
Product Line 28F = Micron Flash memory
Density 512 = 512Mb
00A = 1Gb
00B = 2Gb
Product Family P33 (VCC = 2.3–3.6V; VCCQ = 2.3–3.6V)
Parameter Location B/T = Bottom/Top parameter
E = Symmetrical Blocks
Lithography F = 65nm
Features *

Note

  1. The last digit is assigned randomly to cover packaging media, features, or other specific configuration information. Sample part number: JS28F512P33EF*

Table 2. Standard Part Numbers
Density Configuration Medium JS PC
512Mb Bottom boot Tray JS28F512P33BFD PC28F512P33BFD
Tape & Reel
Top boot Tray JS28F512P33TFA PC28F512P33TFA
Tape & Reel
Uniform Tray JS28F512P33EFA PC28F512P33EFA
Tape & Reel
1Gb Bottom boot Tray JS28F00AP33BFA PC28F00AP33BFA
Tape & Reel
Top boot Tray JS28F00AP33TFA PC28F00AP33TFA
Tape & Reel
Uniform Tray JS28F00AP33EFA PC28F00AP33EFA
Tape & Reel
2Gb Uniform Tray PC28F00BP33EFA
Tape & Reel

Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

General Description

General Description

The Micron Parallel NOR Flash memory is the latest generation of Flash memory devices. Benefits include more density in less space, high-speed interface device, and support for code and data storage. Features include high-performance synchronous-burst read mode, fast asynchronous access times, low power, flexible security options, and three industry-standard package choices. The product family is manufactured using Micron 65nm process technology.

The NOR Flash device provides high performance at low voltage on a 16-bit data bus. Individually erasable memory blocks are sized for optimum code and data storage.

Upon initial power up or return from reset, the device defaults to asynchronous page-mode read. Configuring the read configuration register enables synchronous burst-mode reads. In synchronous burst mode, output data is synchronized with a user-supplied clock signal. A WAIT signal provides easy CPU-to-flash memory synchronization.

In addition to the enhanced architecture and interface, the device incorporates technology that enables fast factory PROGRAM and ERASE operations. Designed for low-voltage systems, the devIce supports READ operations with VCC at the low voltages, and ERASE and PROGRAM operations with VPP at the low voltages or VPPH. Buffered enhanced factory programming (BEFP) provides the fastest Flash array programming performance with VPP at VPPH, which increases factory throughput. With VPP at low voltages, VCC and VPP can be tied together for a simple, ultra low-power design. In addition to voltage flexibility, a dedicated VPP connection provides complete data protection when VPP ≤ VPPLK.

A command user interface is the interface between the system processor and all internal operations of the device. The device automatically executes the algorithms and timings necessary for block erase and program. A status register indicates ERASE or PROGRAM completion and any errors that may have occurred.

An industry-standard command sequence invokes program and erase automation. Each ERASE operation erases one block. The erase suspend feature enables system software to pause an ERASE cycle to read or program data in another block. Program suspend enables system software to pause programming to read other locations. Data is programmed in word increments (16 bits).

The protection register enables unique device identification that can be used to increase system security. The individual block lock feature provides zero-latency block locking and unlocking. The device includes enhanced protection via password access; this new feature supports write and/or read access protection of user-defined blocks. In addition, the device also provides the full-device OTP security feature.

Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

Virtual Chip Enable Description

Virtual Chip Enable Description

The 2Gb device employs a virtual chip enable feature, which combines two 1Gb die with a common chip enable, CE# for Easy BGA packages. The maximum address bit is then used to select between the die pair with CE# asserted. When CE# is asserted and the maximum address bit is LOW, the lower parameter die is selected; when CE# is asserted and the maximum address bit is HIGH, the upper parameter die is selected.

Table 1. Virtual Chip Enable Truth Table for Easy BGA Packages
Die Selected CE# A[MAX]
Lower parameter die L L
Upper parameter die L H
Figure 1. Easy BGA Block Diagram


Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.