inputs: Provide the row address for ACTIVATE commands and the column
address for READ/WRITE commands in order to select one location out of the
memory array in the respective bank (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, and
RAS_n/A16 have additional functions; see individual entries in this table). The
address inputs also provide the op-code during the MODE REGISTER SET command.
A17 is only defined for x4 SDRAM.
||Auto precharge: A10 is
sampled during READ and WRITE commands to determine whether an auto precharge
should be performed on the accessed bank after a READ or WRITE operation (HIGH
= auto precharge; LOW = no auto precharge). A10 is sampled during a PRECHARGE
command to determine whether the precharge applies to one bank (A10 LOW) or all
banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by
the bank group and bank addresses.
||Burst chop: A12/BC_n is
sampled during READ and WRITE commands to determine if burst chop (on-the-fly)
will be performed (HIGH = no burst chop; LOW = burst- chopped). See Command
Truth Table in the DDR4 component data sheet.
||Command input: ACT_n
defines the ACTIVATE command being entered along with CS_n. The input into
RAS_n/A16, CAS_n/A15, and WE_n/A14 are considered as row address A16, A15, and
A14. See Command Truth Table.
inputs: Define the bank (with a bank group) to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. Also determine which mode
register is to be accessed during a MODE REGISTER SET command.
||Bank group address
inputs: Define the bank group to which a REFRESH, ACTIVATE, READ, WRITE, or
PRECHARGE command is being applied. Also determine which mode register is to be
accessed during a MODE REGISTER SET command. BG[1:0] are used in the x4 and x8
configurations. x16-based SDRAM only has BG0.
|C0, C1, C2
||Chip ID: These inputs are
used only when devices are stacked; that is, 2H, 4H, and 8H stacks for x4 and
x8 configurations using through-silicon vias (TSVs). These pins are not used in
the x16 configuration. Some DDR4 modules support a traditional DDP package,
which uses CS1_n, CKE1, and ODT1 to control the second die. All other stack
configurations, such as a 4H or 8H, are assumed to be single-load
(master/slave) type configurations where C0, C1, and C2 are used as chip ID
selects in conjunction with a single CS_n, CKE, and ODT. Chip ID is considered
part of the command code.
Differential clock inputs. All address, command, and control input signals are
sampled on the crossing of the positive edge of CK_t and the negative edge of
enable: CKE HIGH activates and CKE LOW deactivates the internal clock
signals, device input buffers, and output drivers. Taking CKE LOW provides
PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or active
power-down (row active in any bank). CKE is asynchronous for self refresh exit.
After VREFCA has
become stable during the power-on and initialization sequence, it must be
maintained during all operations (including SELF REFRESH). CKE must be
maintained HIGH throughout read and write accesses. Input buffers (excluding
CK_t, CK_c, ODT, RESET_n, and CKE) are disabled during power-down. Input
buffers (excluding CKE and RESET#) are disabled during self refresh.
select: All commands are masked when CS_n is registered HIGH. CS_n provides
external rank selection on systems with multiple ranks. CS_n is considered part
of the command code (CS2_n and CS3_n are not used on UDIMMs).
termination: ODT (registered HIGH) enables termination resistance internal
to the DDR4 SDRAM. When enabled, ODT (RTT) is applied only to each DQ, DQS_t, DQS_c,
DM_n/DBI_n/TDQS_t, and TDQS_c signal for x4 and x8 configurations (when the
TDQS function is enabled via the mode register). For the x16 configuration,
RTT is applied to
each DQ, DQSU_t, DQSU_c, DQSL_t, DQSL_c, UDM_n, and LDM_n signal. The ODT pin
will be ignored if the mode registers are programmed to disable RTT.
||Parity for command and
address: This function can be enabled or disabled via the mode register.
When enabled in MR5, the DRAM calculates parity with ACT_n, RAS_n/A16,
CAS_n/A15, WE_n/A14, BG[1:0], BA[1:0], A[16:0]. Input parity should be
maintained at the rising edge of the clock and at the same time as command and
address with CS_n LOW.
inputs: RAS_n/A16, CAS_n/A15, and WE_n/A14 (along with CS_n) define the
command and/or address being entered and have multiple functions. For example,
for activation with ACT_n LOW, these are addresses like A16, A15, and A14, but
for a non-activation command with ACT_n HIGH, these are command pins for READ,
WRITE, and other commands defined in Command Truth Table.
|| CMOS Input
asynchronous reset: Reset is active when RESET_n is LOW and inactive when
RESET_n is HIGH. RESET_n must be HIGH during normal operation.
||Serial address inputs:
Used to configure the temperature sensor/SPD EEPROM address range on the I2C bus.
||Serial clock for temperature
sensor/SPD EEPROM: Used to synchronize communication to and from the
temperature sensor/SPD EEPROM on the I2C bus.
| DQx, CBx
input/output and check bit input/output: Bidirectional data bus. DQ
represents DQ[3:0], DQ[7:0], and DQ[15:0] for the x4, x8, and x16
configurations, respectively. If cyclic redundancy checksum (CRC) is enabled
via the mode register, the CRC code is added at the end of the data burst. Any
one or all of DQ0, DQ1, DQ2, or DQ3 may be used for monitoring of internal
VREF level during
test via mode register setting MR A = HIGH; training times change when
mask and data bus inversion:
DM_n is an input mask signal for write data. Input data is
masked when DM_n is sampled LOW coincident with that input data during a write
access. DM_n is sampled on both edges of DQS. DM is multiplexed with the DBI
function by the mode register A10, A11, and A12 settings in MR5. For a x8
device, the function of DM or TDQS is enabled by the mode register A11 setting
in MR1. DBI_n is an input/output identifying whether to store/output the true
or inverted data. If DBI_n is LOW, the data will be stored/output after
inversion inside the DDR4 device and not inverted if DBI_n is HIGH. TDQS is
only supported in x8 SDRAM configurations (TDQS is not valid for UDIMMs).
Bidirectional signal used to transfer data in or out of the EEPROM or EEPROM/TS
strobe: Output with read data, input with write data. Edge-aligned with
read data, centered-aligned with write data. For x16 configurations, DQSL
corresponds to the data on DQ[7:0], and DQSU corresponds to the data on
DQ[15:8]. For the x4 and x8 configurations, DQS corresponds to the data on
DQ[3:0] and DQ[7:0], respectively. DDR4 SDRAM supports a differential data
strobe only and does not support a single-ended data strobe.
||Alert output: Possesses
functions such as CRC error flag and command and address parity error flag as
output signal. If a CRC error occurs, ALERT_n goes LOW for the period time
interval and returns HIGH. If an error occurs during a command address parity
check, ALERT_n goes LOW until the on-going DRAM internal recovery transaction
is complete. During connectivity test mode, this pin functions as an input. Use
of this signal is system-dependent. If not connected as signal, ALERT_n pin
must be connected to VDD on DIMMs.
||Temperature event: The
EVENT_n pin is asserted by the temperature sensor when critical temperature
thresholds have been exceeded. This pin has no function (NF) on modules without
DRAM-based RDIMM only)
data strobe: When enabled via the mode register, the DRAM device enables
the same RTT
termination resistance on TDQS_t and TDQS_c that is applied to DQS_t and DQS_c.
When the TDQS function is disabled via the mode register, the DM/TDQS_t pin
provides the data mask (DM) function, and the TDQS_c pin is not used. The TDQS
function must be disabled in the mode register for both the x4 and x16
configurations. The DM function is supported only in x8 and x16 configurations.
DM, DBI, and TDQS are a shared pin and are enabled/disabled by mode register
settings. For more information about TDQS, see the DDR4 DRAM component data
sheet (TDQS_t and TDQS_c are not valid for UDIMMs).
supply: 1.2V (TYP).
||DRAM activating power
supply: 2.5V –0.125V / +0.250V.
|| Reference voltage for
control, command, and address pins.
||Power supply for termination
of address, command, and control VDD/2.
||Power supply used to power
the I2C bus for
||Reserved for future use.
connect: No internal electrical connection is present.
function: May have internal connection present, but has no function.