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Data Sheet Uploaded 07/2015

Parts associated with this datasheet:
MT16KTF1G64HZ-1G6 MT16KTF1G64HZ-1G9
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Features

Features


  • DDR3L functionality and operations supported as defined in the component data sheet
  • 204-pin, small outline dual in-line memory module (SODIMM)
  • Fast data transfer rates: PC3-14900, PC3-12800, PC3-10600, PC3-8500, or PC3-6400
  • 2GB (256 Meg x 64), 4GB (512 Meg x 64), 8GB (1 Gig x 64)
  • VDD = 1.35V (1.283V–1.45V)
  • VDD = 1.5V (1.425–1.575V)
  • Backward compatible to VDD = 1.5V ±0.075V
  • VDDSPD = 3.0–3.6V
  • Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
  • Dual rank
  • Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS)
  • On-board I2C serial presence-detect (SPD) EEPROM
  • Selectable BC4 or BL8 on-the-fly (OTF)
  • Gold edge contacts
  • Halogen-free
  • Fly-by topology
  • Terminated control, command, and address bus
Figure 1. 204-Pin SODIMM (MO-268 R/C-F,
R/C-F3)


Options Marking

Operating temperature

 

Commercial (0°C ≤ TA ≤ +70°C)

None

Package

 

204-pin DIMM (halogen-free)

Z

Frequency/CAS latency

 

1.07ns @ CL = 13 (DDR3-1866)

-1G9

1.25ns @ CL = 11 (DDR3-1600)

-1G6

1.5ns @ CL = 9 (DDR3-1333)

-1G4

1.87ns @ CL = 7 (DDR3-1066)

-1G1
Table 1. Key Timing Parameters
Speed Grade Industry
Nomenclature
Data Rate (MT/s) tRCD
(ns)
tRP
(ns)
tRC
(ns)
CL = 13 CL = 11 CL = 10 CL = 9 CL = 8 CL = 7 CL = 6 CL = 5
-1G9 PC3-14900 1866 1600 1333 1333 1066 1066 800 667 13.125 13.125 47.125
-1G6 PC3-12800 1600 1333 1333 1066 1066 800 667 13.125 13.125 48.125
-1G4 PC3-10600 1333 1333 1066 1066 800 667 13.125 13.125 49.125
-1G1 PC3-8500 1066 1066 800 667 13.125 13.125 50.625
-1G0 PC3-8500 1066 800 667 15 15 52.5
-80B PC3-6400 800 667 15 15 52.5
Table 2. Addressing
Parameter 2GB 4GB 8GB
Refresh count 8K 8K 8K
Row address 16K A[13:0] 32K A[14:0] 64K A[15:0]
Device bank address 8 BA[2:0] 8 BA[2:0] 8 BA[2:0]
Device configuration 1Gb (128 Meg x 8) 2Gb (256 Meg x 8) 4Gb (512 Meg x8)
Column address 1K A[9:0] 1K A[9:0] 1K A[9:0]
Module rank address 2 S#[1:0] 2 S#[1:0] 2 S#[1:0]
Table 3. Part Numbers and Timing Parameters – 2GB Modules

Base device: MT41K128M8, 1Gb 1.35V DDR3L SDRAM

Part Number Module
Density
Configuration Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
MT16KTF25664HZ-1G6__ 2GB 256 Meg x 64 12.8 GB/s 1.25ns/1600 MT/s 11-11-11
MT16KTF25664HZ-1G4__ 2GB 256 Meg x 64 10.6 GB/s 1.5ns/1333 MT/s 9-9-9
MT16KTF25664HZ-1G1__ 2GB 256 Meg x 64 8.5 GB/s 1.87ns/1066 MT/s 7-7-7
Table 4. Part Numbers and Timing Parameters – 4GB Modules

Base device: MT41K256M8, 2Gb 1.35V DDR3L SDRAM

Part Number Module
Density
Configuration Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
MT16KTF51264HZ-1G6__ 4GB 512 Meg x 64 12.8 GB/s 1.25ns/1600 MT/s 11-11-11
MT16KTF51264HZ-1G4__ 4GB 512 Meg x 64 10.6 GB/s 1.5ns/1333 MT/s 9-9-9
MT16KTF51264HZ-1G1__ 4GB 512 Meg x 64 8.5 GB/s 1.87ns/1066 MT/s 7-7-7
Table 5. Part Numbers and Timing Parameters – 8GB Modules

Base device: MT41K512M8, 4Gb 1.35V DDR3L SDRAM

Part Number2 Module
Density
Configuration Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
MT16KTF1G64HZ-1G9__ 8GB 1 Gig x 64 14.9 GB/s 1.07ns/1866 MT/s 13-13-13
MT16KTF1G64HZ-1G6__ 8GB 1 Gig x 64 12.8 GB/s 1.25ns/1600 MT/s 11-11-11
MT16KTF1G64HZ-1G4__ 8GB 1 Gig x 64 10.6 GB/s 1.5ns/1333 MT/s 9-9-9
MT16KTF1G64HZ-1G1__ 8GB 1 Gig x 64 8.5 GB/s 1.87ns/1066 MT/s 7-7-7

Notes

  1. The data sheet for the base device can be found on Micron’s Web site.

  2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT16KTF1G64HZ-1G9N1.

Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

Pin Assignments

Pin Assignments

Table 1. Pin Assignments

204-Pin DDR3 SODIMM Front 204-Pin DDR3 SODIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1 VREFDQ 53 DQ19 105 VDD 157 DQ42 2 VSS 54 VSS 106 VDD 158 DQ46
3 VSS 55 VSS 107 A10 159 DQ43 4 DQ4 56 DQ28 108 BA1 160 DQ47
5 DQ0 57 DQ24 109 BA0 161 VSS 6 DQ5 58 DQ29 110 RAS# 162 VSS
7 DQ1 59 DQ25 111 VDD 163 DQ48 8 VSS 60 VSS 112 VDD 164 DQ52
9 VSS 61 VSS 113 WE# 165 DQ49 10 DQS0# 62 DQS3# 114 S0# 166 DQ53
11 DM0 63 DM3 115 CAS# 167 VSS 12 DQS0 64 DQS3 116 ODT0 168 VSS
13 VSS 65 VSS 117 VDD 169 DQS6# 14 VSS 66 VSS 118 VDD 170 DM6
15 DQ2 67 DQ26 119 A13 171 DQS6 16 DQ6 68 DQ30 120 ODT1 172 VSS
17 DQ3 69 DQ27 121 S1# 173 VSS 18 DQ7 70 DQ31 122 NC 174 DQ54
19 VSS 71 VSS 123 VDD 175 DQ50 20 VSS 72 VSS 124 VDD 176 DQ55
21 DQ8 73 CKE0 125 NC 177 DQ51 22 DQ12 74 CKE1 126 VREFCA 178 VSS
23 DQ9 75 VDD 127 VSS 179 VSS 24 DQ13 76 VDD 128 VSS 180 DQ60
25 VSS 77 NC 129 DQ32 181 DQ56 26 VSS 78 NC/A151 130 DQ36 182 DQ61
27 DQS1# 79 BA2 131 DQ33 183 DQ57 28 DM1 80 NC/A142 132 DQ37 184 VSS
29 DQS1 81 VDD 133 VSS 185 VSS 30 RESET# 82 VDD 134 VSS 186 DQS7#
31 VSS 83 A12 135 DQS4# 187 DM7 32 VSS 84 A11 136 DM4 188 DQS7
33 DQ10 85 A9 137 DQS4 189 VSS 34 DQ14 86 A7 138 VSS 190 VSS
35 DQ11 87 VDD 139 VSS 191 DQ58 36 DQ15 88 VDD 140 DQ38 192 DQ62
37 VSS 89 A8 141 DQ34 193 DQ59 38 VSS 90 A6 142 DQ39 194 DQ63
39 DQ16 91 A5 143 DQ35 195 VSS 40 DQ20 92 A4 144 VSS 196 VSS
41 DQ17 93 VDD 145 VSS 197 SA0 42 DQ21 94 VDD 146 DQ44 198 NF
43 VSS 95 A3 147 DQ40 199 VDDSPD 44 VSS 96 A2 148 DQ45 200 SDA
45 DQS2# 97 A1 149 DQ41 201 SA1 46 DM2 98 A0 150 VSS 202 SCL
47 DQS2 99 VDD 151 VSS 203 VTT 48 VSS 100 VDD 152 DQS5# 204 VTT
49 VSS 101 CK0 153 DM5 50 DQ22 102 CK1 154 DQS5
51 DQ18 103 CK0# 155 VSS 52 DQ23 104 CK1# 156 VSS

Notes

  1. Pin 78 is NC for 2GB and 4GB, A15 for 8GB.

  2. Pin 80 is NC for 2GB, A14 for 4GB and 8GB.

Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

Pin Descriptions

Pin Descriptions

The pin description table below is a comprehensive list of all possible pins for all DDR3 modules. All pins listed may not be supported on this module. See Pin Assignments for information specific to this module.

Table 1. Pin Descriptions
Symbol Type Description
Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. See the Pin Assignments table for density-specific addressing information.
BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command.
CKx,
CKx#
Input Clock: Differential clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#.
CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM.
DMx Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write access. Although DM pins are input-only, DM loading is designed to match that of the DQ and DQS pins.
ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input will be ignored if disabled via the LOAD MODE command.
Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered.
RESET# Input
(LVCMOS)
Reset: RESET# is an active LOW asychronous input that is connected to each DRAM and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitialized as though a normal power-up was executed.
Sx# Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command decoder.
SAx Input Serial address inputs: Used to configure the temperature sensor/SPD EEPROM address range on the I2C bus.
SCL Input Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communication to and from the temperature sensor/SPD EEPROM on the I2C bus.
CBx I/O Check bits: Used for system error detection and correction.
DQx I/O Data input/output: Bidirectional data bus.
DQSx,
DQSx#
I/O Data strobe: Differential data strobes. Output with read data; edge-aligned with read data; input with write data; center-aligned with write data.
SDA I/O Serial data: Used to transfer addresses and data into and out of the temperature sensor/SPD EEPROM on the I2C bus.
TDQSx,
TDQSx#
Output Redundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD MODE command to the extended mode register (EMR). When TDQS is enabled, DM is disabled and TDQS and TDQS# provide termination resistance; otherwise, TDQS# are no function.
Err_Out# Output
(open drain)
Parity error output: Parity error found on the command and address bus.
EVENT# Output
(open drain)
Temperature event: The EVENT# pin is asserted by the temperature sensor when critical temperature thresholds have been exceeded.
VDD Supply Power supply: 1.35V (1.283–1.45V) backward-compatible to 1.5V (1.425–1.575V). The component VDD and VDDQ are connected to the module VDD.
VDDSPD Supply Temperature sensor/SPD EEPROM power supply: 3.0–3.6V.
VREFCA Supply Reference voltage: Control, command, and address VDD/2.
VREFDQ Supply Reference voltage: DQ, DM VDD/2.
VSS Supply Ground.
VTT Supply Termination voltage: Used for control, command, and address VDD/2.
NC No connect: These pins are not connected on the module.
NF No function: These pins are connected within the module, but provide no functionality.

Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.