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Data Sheet Uploaded 12/2009

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Features

Features


  • 240-pin, DDR2 fully buffered DIMM (FBDIMM)
  • Fast data transfer rates: PC2-4200, PC2-5300, or PC2-6400
  • 512MB (64 Meg x 72), 1GB (128 Meg x 72)
  • 3.2 Gb/s, 4.0 Gb/s, and 4.8 Gb/s link transfer rates
  • High-speed, 1.5V differential, point-to-point link between host memory controller and the advanced memory buffer (AMB)
  • Fault-tolerant; can work around a bad bit lane in each direction
  • High-density scaling with up to eight FBDIMM devices per channel
  • SMBus interface to AMB for configuration register access
  • In-band and out-of-band command access
  • Deterministic protocol
    • Enables memory controller to optimize DRAM accesses for maximum performance
    • Delivers precise control and repeatable memory behavior
  • Automatic DDR2 SDRAM bus and channel calibration
  • Transmitter de-emphasis to reduce ISI
  • MBIST and IBIST test functions
  • Transparent mode for DRAM test support
  • VDD = VDDQ = 1.8V for DRAM
  • VREF = 0.9V SDRAM command and address termination
  • VCC = 1.5V for AMB
  • VDDSPD = 3–3.6V for AMB and EEPROM
  • Serial presence-detect (SPD) with EEPROM
  • Gold edge contacts
  • Single rank
  • Supports 95°C operation with 2X refresh
Figure 1. 240-Pin FBDIMM (MO-256 R/C A)

Options Marking

Package

 

240-pin DIMM (Pb-free)

Y

Frequency/CAS latency

 

2.5ns @ CL = 5 (DDR2-800)

-80E

3.0ns @ CL = 5 (DDR2-667)

-667

3.75ns @ CL = 4 (DDR2-533)1

-53E

Note

  1. Not recommended for new designs.

Table 1. Key Timing Parameters
Speed Grade Industry
Nomenclature
Data Rate (MT/s) tRCD (ns) tRP (ns) tRC (ns)
CL = 5 CL = 4 CL = 3
-80E PC2-6400 800 533 12.5 12.5 55
-667 PC2-5300 667 533 400 15 15 55
-53E PC2-4200 533 400 15 15 55
Table 2. Addressing
Parameter 512MB 1GB
Refresh count 8K 8K
Device bank address 4 BA[1:0] 8 BA[2:0]
Device configuration 512Mb (64 Meg x 8) 1Gb (128 Meg x 8)
Row address 16K A[13:0] 16K A[13:0]
Column address 1K A[9:0] 1K A[9:0]
Module rank address 1 S0# 1 S0#
Table 3. Part Numbers and Timing Parameters – 512MB

Base device: MT47H64M8, 512Mb DDR2 SDRAM

Part Number Module Density Configuration Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
Link Transfer Rate
MT9HTF6472FY-80E__ 512MB 64 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5 4.8 GT/s
MT9HTF6472FY-667__ 512MB 64 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5 4.0 GT/s
MT9HTF6472FY-53E__ 512MB 64 Meg x 72 4.3 GB/s 3.75ns/533 MT/s 4-4-4 3.2 GT/s
Table 4. Part Numbers and Timing Parameters – 1GB

Base device: MT47H128M8, 1Gb DDR2 SDRAM

Part Number2 Module Density Configuration Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
Link Transfer Rate
MT9HTF12872FY-80E__ 1GB 128 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5 4.8 GT/s
MT9HTF12872FY-667__ 1GB 128 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5 4.0 GT/s
MT9HTF12872FY-53E__ 1GB 128 Meg x 72 4.3 GB/s 3.75ns/533 MT/s 4-4-4 3.2 GT/s

Notes

  1. The data sheet for the base device can be found on Micron’s Web site.

  2. All part numbers end with a four-place code (not shown) that designates component, PCB, and AMB revisions. Consult factory for current revision codes. Example: MT9HTF12872FY-667E1D4.

Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

Pin Assignments and Descriptions

Pin Assignments and Descriptions

Table 1. Pin Assignments

240-Pin FBDIMM Front 240-Pin FBDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1 VDD 31 PN3 61 PN9# 91 PS9#1 121 VDD 151 SN3 181 SN9# 211 SS9#1
2 VDD 32 PN3# 62 VSS 92 VSS 122 VDD 152 SN3# 182 VSS 212 VSS
3 VDD 33 VSS 63 PN10 93 PS5 123 VDD 153 VSS 183 SN10 213 SS5
4 VSS 34 PN4 64 PN10# 94 PS5# 124 VSS 154 SN4 184 SN10# 214 SS5#
5 VDD 35 PN4# 65 VSS 95 VSS 125 VDD 155 SN4# 185 VSS 215 VSS
6 VDD 36 VSS 66 PN11 96 PS6 126 VDD 156 VSS 186 SN11 216 SS6
7 VDD 37 PN5 67 PN11# 97 PS6# 127 VDD 157 SN5 187 SN11# 217 SS6#
8 VSS 38 PN5# 68 VSS 98 VSS 128 VSS 158 SN5# 188 VSS 218 VSS
9 VCC 39 VSS 69 VSS 99 PS7 129 VCC 159 VSS 189 VSS 219 SS7
10 VCC 40 PN131 70 PS0 100 PS7# 130 VCC 160 SN131 190 SS0 220 SS7#
11 VSS 41 PN13#1 71 PS0# 101 VSS 131 VSS 161 SN13#1 191 SS0# 221 VSS
12 VCC 42 VSS 72 VSS 102 PS8 132 VCC 162 VSS 192 VSS 222 SS8
13 VCC 43 VSS 73 PS1 103 PS8# 133 VCC 163 VSS 193 SS1 223 SS8#
14 VSS 44 DNU 74 PS1# 104 VSS 134 VSS 164 DNU 194 SS1# 224 VSS
15 VTT 45 DNU 75 VSS 105 DNU 135 VTT 165 DNU 195 VSS 225 DNU
16 DNU 46 VSS 76 PS2 106 DNU 136 DNU 166 VSS 196 SS2 226 DNU
17 RESET# 47 VSS 77 PS2# 107 VSS 137 M_TEST (DNU) 167 VSS 197 SS2# 227 VSS
18 VSS 48 PN121 78 VSS 108 VDD 138 VSS 168 SN121 198 VSS 228 SCK
19 DNU 49 PN12#1 79 PS3 109 VDD 139 DNU 169 SN12#1 199 SS3 229 SCK#
20 DNU 50 VSS 80 PS3# 110 VSS 140 DNU 170 VSS 200 SS3# 230 VSS
21 VSS 51 PN6 81 VSS 111 VDD 141 VSS 171 SN6 201 VSS 231 VDD
22 PN0 52 PN6# 82 PS4 112 VDD 142 SN0 172 SN6# 202 SS4 232 VDD
23 PN0# 53 VSS 83 PS4# 113 VDD 143 SN0# 173 VSS 203 SS4# 233 VDD
24 VSS 54 PN7 84 VSS 114 VSS 144 VSS 174 SN7 204 VSS 234 VSS
25 PN1 55 PN7# 85 VSS 115 VDD 145 SN1 175 SN7# 205 VSS 235 VDD
26 PN1# 56 VSS 86 DNU 116 VDD 146 SN1# 176 VSS 206 NC 236 VDD
27 VSS 57 PN8 87 DNU 117 VTT 147 VSS 177 SN8 207 NC 237 VTT
28 PN2 58 PN8# 88 VSS 118 SA2 148 SN2 178 SN8# 208 VSS 238 VDDSPD
29 PN2# 59 VSS 89 VSS 119 SDA 149 SN2# 179 VSS 209 VSS 239 SA0
30 VSS 60 PN9 90 PS91 120 SCL 150 VSS 180 SN9 210 SS91 240 SA1

Note

  1. The following signals are cyclical redundancy code (CRC) bits and thus appear out of the normal sequence: PN12/PN12#, SN12/SN12#, PN13/PN13#, SN13/SN13#, PS9/PS9#, and SS9/SS9#.

Table 2. Pin Descriptions
Symbol Type Description
PS[9:0] Input Primary southbound data, positive lines.
PS#[9:0] Input Primary southbound data, negative lines.
SCK Input System clock input, positive line.
SCK# Input System clock input, negative line.
SCL Input Serial presence-detect (SPD) clock input.
SS[9:0] Input Secondary southbound data, positive lines.
SS#[9:0] Input Secondary southbound data, negative lines.
PN[13:0] Output Primary northbound data, positive lines.
PN#[13:0] Output Primary northbound data, negative lines.
SN[13:0] Output Secondary northbound data, positive lines.
SN#[13:0] Output Secondary northbound data, negative lines.
SA[2:0] I/O SPD address inputs, also used to select the FBDIMM number in the AMB.
SDA I/O SPD data input/output.
RESET# Supply AMB reset signal.
VCC Supply AMB core power and AMB channel interface power (1.5V).
VDD Supply DRAM power and AMB DRAM I/O power (1.8V).
VTT Supply DRAM clock, command, and address termination power (VDD/2).
VDDSPD Supply SPD/AMB SMBus power (3.3V).
VSS Supply Ground.
M_TEST The M_TEST pin provides an external connection for testing the margin of VREF, which is produced by a voltage divider on the module. It is not intended to be used in normal system operation and must not be connected (DNU) in a system. This test pin may have other features on future card designs and will be included in this specification at that time.
DNU Do not use.

Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

System Block Diagram

System Block Diagram

Figure 1. System Block Diagram


Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.