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Data Sheet Uploaded 03/2010

Parts associated with this datasheet:
MT4HTF1664AY-40E MT4HTF1664AY-53E MT4HTF1664AY-667
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Features

Features


  • 240-pin, unbuffered dual in-line memory module (UDIMM)
  • Fast data transfer rates: PC2-3200, PC2-4200, PC2-5300, or PC2-6400
  • 128MB (16 Meg x 64), 256MB (32 Meg x 64),
    512MB (64 Meg x 64)
  • VDD = VDDQ = 1.8V
  • VDDSPD = 1.7–3.6V
  • JEDEC-standard 1.8V I/O (SSTL_18-compatible)
  • Differential data strobe (DQS, DQS#) option
  • 4n-bit prefetch architecture
  • Multiple internal device banks for concurrent
    operation
  • Programmable CAS latency (CL)
  • Posted CAS additive latency (AL)
  • WRITE latency = READ latency - 1 tCK
  • Programmable burst lengths (BL): 4 or 8
  • Adjustable data-output drive strength
  • 64ms, 8192-cycle refresh
  • On-die termination (ODT)
  • Serial presence detect (SPD) with EEPROM
  • Gold edge contacts
  • Single rank
Figure 1. 240-Pin UDIMM (MO-237 R/C C)

Options Marking

Operating temperature

 

Commercial (0°C ≤ TA ≤ +70°C)

None

Industrial (–40°C ≤ TA ≤ +85°C)1

I

Package

 

240-pin DIMM (lead-free)

Y

Frequency/CL2

 

2.5ns @ CL = 5 (DDR2-800)4

-80E

2.5ns @ CL = 6 (DDR2-800)4

-800

3.0ns @ CL = 5 (DDR2-667)

-667

3.75ns @ CL = 4 (DDR2-533)3

-53E

5.0ns @ CL = 3 (DDR2-400)3

-40E

Notes

  1. Contact Micron for industrial temperature module offerings.

  2. CL = CAS (READ) latency.

  3. Contact Micron for product availability.

  4. Not available in 128MB and 256MB.

Table 1. Key Timing Parameters
Speed Grade Industry
Nomenclature
Data Rate (MT/s) tRCD
(ns)
tRP
(ns)
tRC
(ns)
CL = 6 CL = 5 CL = 4 CL = 3
-80E PC2-6400 800 800 533 400 12.5 12.5 55
-800 PC2-6400 800 667 533 400 15 15 55
-667 PC2-5300 667 553 400 15 15 55
-53E PC2-4200 553 400 15 15 55
-40E PC2-3200 400 400 15 15 55
Table 2. Addressing
Parameter 128MB 256MB 512MB
Refresh count 8K 8K 8K
Row address 8K A[12:0] 8K A[12:0] 8K A[12:0]
Device bank address 4 BA[1:0] 4 BA[1:0] 8 BA[2:0]
Device configuration 256Mb (16 Meg x 16) 512Mb (32 Meg x 16) 1Gb (64 Meg x 16)
Column address 512 A[8:0] 1K A[9:0] 1K A[9:0]
Module rank address 1 S0# 1 S0# 1 S0#
Table 3. Part Numbers and Timing Parameters – 128MB Modules (End of Life)

Base device: MT47H16M16, 256Mb DDR2 SDRAM

Part Number Module
Density
Configuration Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
MT4HTF1664A(I)Y-667__ 128MB 16 Meg x 64 5.3 GB/s 3.0ns/667 MT/s 5-5-5
MT4HTF1664A(I)Y-53E__ 128MB 16 Meg x 64 4.3 GB/s 3.75ns/533 MT/s 4-4-4
MT4HTF1664A(I)Y-40E__ 128MB 16 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3
Table 4. Part Numbers and Timing Parameters – 256MB Modules

Base device: MT47H32M16, 512Mb DDR2 SDRAM

Part Number Module
Density
Configuration Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
MT4HTF3264A(I)Y-80E__ 256MB 32 Meg x 64 6.4 GB/s 2.5ns/800 MT/s 5-5-5
MT4HTF3264A(I)Y-800__ 256MB 32 Meg x 64 6.4 GB/s 2.5ns/800 MT/s 6-6-6
MT4HTF3264A(I)Y-667__ 256MB 32 Meg x 64 5.3 GB/s 3.0ns/667 MT/s 5-5-5
MT4HTF3264A(I)Y-53E__ 256MB 32 Meg x 64 4.3 GB/s 3.75ns/533 MT/s 4-4-4
MT4HTF3264A(I)Y-40E__ 256MB 32 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3
Table 5. Part Numbers and Timing Parameters – 512MB Modules

Base device: MT47H64M16, 1Gb DDR2 SDRAM

Part Number2 Module
Density
Configuration Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
MT4HTF6464A(I)Y-80E__ 512MB 64 Meg x 64 6.4 GB/s 2.5ns/800 MT/s 5-5-5
MT4HTF6464A(I)Y-800__ 512MB 64 Meg x 64 6.4 GB/s 2.5ns/800 MT/s 6-6-6
MT4HTF6464A(I)Y-667__ 512MB 64 Meg x 64 5.3 GB/s 3.0ns/667 MT/s 5-5-5
MT4HTF6464A(I)Y-53E__ 512MB 64 Meg x 64 4.3 GB/s 3.75ns/533 MT/s 4-4-4
MT4HTF6464A(I)Y-40E__ 512MB 64 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3

Notes

  1. The data sheet for the base device can be found on Micron’s Web site.

  2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.
    Consult factory for current revision codes. Example: MT4HTF3264AY-667E1.

UNKNOWN

Pin Assignments

Pin Assignments

Table 1. Pin Assignments

240-Pin UDIMM Front 240-Pin UDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1 VREF 31 DQ19 61 A4 91 VSS 121 VSS 151 VSS 181 VDDQ 211 DM5
2 VSS 32 VSS 62 VDDQ 92 DQS5# 122 DQ4 152 DQ28 182 A3 212 NC
3 DQ0 33 DQ24 63 A2 93 DQS5 123 DQ5 153 DQ29 183 A1 213 VSS
4 DQ1 34 DQ25 64 VDD 94 VSS 124 VSS 154 VSS 184 VDD 214 DQ46
5 VSS 35 VSS 65 VSS 95 DQ42 125 DM0 155 DM3 185 CK0 215 DQ47
6 DQS0# 36 DQS3# 66 VSS 96 DQ43 126 NC 156 NC 186 CK0# 216 VSS
7 DQS0 37 DQS3 67 VDD 97 VSS 127 VSS 157 VSS 187 VDD 217 DQ52
8 VSS 38 VSS 68 NC 98 DQ48 128 DQ6 158 DQ30 188 A0 218 DQ53
9 DQ2 39 DQ26 69 VDD 99 DQ49 129 DQ7 159 DQ31 189 VDD 219 VSS
10 DQ3 40 DQ27 70 A10 100 VSS 130 VSS 160 VSS 190 BA1 220 CK2
11 VSS 41 VSS 71 BA0 101 SA2 131 DQ12 161 NC 191 VDDQ 221 CK2#
12 DQ8 42 NC 72 VDDQ 102 NC 132 DQ13 162 NC 192 RAS# 222 VSS
13 DQ9 43 NC 73 WE# 103 VSS 133 VSS 163 VSS 193 S0# 223 DM6
14 VSS 44 VSS 74 CAS# 104 DQS6# 134 DM1 164 NC 194 VDDQ 224 NC
15 DQS1# 45 NC 75 VDDQ 105 DQS6 135 NC 165 NC 195 ODT0 225 VSS
16 DQS1 46 NC 76 NC 106 VSS 136 VSS 166 VSS 196 NC 226 DQ54
17 VSS 47 VSS 77 NC 107 DQ50 137 CK1 167 NC 197 VDD 227 DQ55
18 NC 48 NC 78 VDDQ 108 DQ51 138 CK1# 168 NC 198 VSS 228 VSS
19 NC 49 NC 79 VSS 109 VSS 139 VSS 169 VSS 199 DQ36 229 DQ60
20 VSS 50 VSS 80 DQ32 110 DQ56 140 DQ14 170 VDDQ 200 DQ37 230 DQ61
21 DQ10 51 VDDQ 81 DQ33 111 DQ57 141 DQ15 171 NC 201 VSS 231 VSS
22 DQ11 52 CKE0 82 VSS 112 VSS 142 VSS 172 VDD 202 DM4 232 DM7
23 VSS 53 VDD 83 DQS4# 113 DQS7# 143 DQ20 173 NC 203 NC 233 NC
24 DQ16 54 NC/BA21 84 DQS4 114 DQS7 144 DQ21 174 NC 204 VSS 234 VSS
25 DQ17 55 NC 85 VSS 115 VSS 145 VSS 175 VDDQ 205 DQ38 235 DQ62
26 VSS 56 VDDQ 86 DQ34 116 DQ58 146 DM2 176 A12 206 DQ39 236 DQ63
27 DQS2# 57 A11 87 DQ35 117 DQ59 147 NC 177 A9 207 VSS 237 VSS
28 DQS2 58 A7 88 VSS 118 VSS 148 VSS 178 VDD 208 DQ44 238 VDDSPD
29 VSS 59 VDD 89 DQ40 119 SDA 149 DQ22 179 A8 209 DQ45 239 SA0
30 DQ18 60 A5 90 DQ41 120 SCL 150 DQ23 180 A6 210 VSS 240 SA1

Note

  1. Pin 54 is NC for 128MB and 256MB or BA2 for 512MB.

UNKNOWN

Pin Descriptions

Pin Descriptions

The pin description table below is a comprehensive list of all possible pins for all DDR2 modules. All pins listed may not be supported on this module. See Pin Assignments for information specific to this module.

Table 1. Pin Descriptions
Symbol Type Description
Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. See the Pin Assignments Table for density-specific addressing information.
BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA define which mode register (MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command.
CKx,
CK#x
Input Clock: Differential clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#.
CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DDR2 SDRAM.
DMx Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write access. Although DM pins are input-only, DM loading is designed to match that of the DQ and DQS pins.
ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR2 SDRAM. When enabled in normal operation, ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input will be ignored if disabled via the LOAD MODE command.
Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered.
RESET# Input Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z.
S#x Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command decoder.
SAx Input Serial address inputs: Used to configure the SPD EEPROM address range on the I2C bus.
SCL Input Serial clock for SPD EEPROM: Used to synchronize communication to and from the SPD EEPROM on the I2C bus.
CBx I/O Check bits. Used for system error detection and correction.
DQx I/O Data input/output: Bidirectional data bus.
DQSx,
DQS#x
I/O Data strobe: Travels with the DQ and is used to capture DQ at the DRAM or the controller. Output with read data; input with write data for source synchronous operation. DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command.
SDA I/O Serial data: Used to transfer addresses and data into and out of the SPD EEPROM on the I2C bus.
RDQSx,
RDQS#x
Output Redundant data strobe (x8 devices only): RDQS is enabled/disabled via the LOAD MODE command to the extended mode register (EMR). When RDQS is enabled, RDQS is output with read data only and is ignored during write data. When RDQS is disabled, RDQS becomes data mask (see DMx). RDQS# is only used when RDQS is enabled and differential data strobe mode is enabled.
Err_Out# Output
(open drain)
Parity error output: Parity error found on the command and address bus.
VDD/VDDQ Supply Power supply: 1.8V ±0.1V. The component VDD and VDDQ are connected to the module VDD.
VDDSPD Supply SPD EEPROM power supply: 1.7–3.6V.
VREF Supply Reference voltage: VDD/2.
VSS Supply Ground.
NC No connect: These pins are not connected on the module.
NF No function: These pins are connected within the module, but provide no functionality.
NU Not used: These pins are not used in specific module configurations/operations.
RFU Reserved for future use.
UNKNOWN