||Address inputs: Provide
the row address for ACTIVE commands, and the column address and auto precharge
bit (A10) for READ/WRITE commands, to select one location out of the memory
array in the respective bank. A10 sampled during a PRECHARGE command determines
whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BAx) or
all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD
MODE command. See the Pin Assignments Table for density-specific addressing
||Bank address inputs:
Define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is
being applied. BA define which mode register (MR0, MR1, MR2, and MR3) is loaded
during the LOAD MODE command.
clock inputs. All control, command, and address input signals are sampled on
the crossing of the positive edge of CK and the negative edge of CK#.
||Clock enable: Enables
(registered HIGH) and disables (registered LOW) internal circuitry and clocks
on the DDR2 SDRAM.
||Data mask (x8 devices
only): DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with that input data, during a write access. Although
DM pins are input-only, DM loading is designed to match that of the DQ and DQS
Enables (registered HIGH) and disables (registered LOW) termination resistance
internal to the DDR2 SDRAM. When enabled in normal operation, ODT is only
applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input will be
ignored if disabled via the LOAD MODE command.
||Parity input: Parity
bit for Ax, RAS#, CAS#, and WE#.
|RAS#, CAS#, WE#
||Command inputs: RAS#,
CAS#, and WE# (along with S#) define the command being entered.
forces all registered outputs LOW when RESET# is LOW. This signal can be used
during power-up to ensure that CKE is LOW and DQ are High-Z.
||Chip select: Enables
(registered LOW) and disables (registered HIGH) the command decoder.
||Serial address inputs:
Used to configure the SPD EEPROM address range on the I2C bus.
||Serial clock for SPD
EEPROM: Used to synchronize communication to and from the SPD EEPROM on the
||Check bits. Used for
system error detection and correction.
Bidirectional data bus.
||Data strobe: Travels
with the DQ and is used to capture DQ at the DRAM or the controller. Output
with read data; input with write data for source synchronous operation. DQS# is
only used when differential data strobe mode is enabled via the LOAD MODE
||Serial data: Used to
transfer addresses and data into and out of the SPD EEPROM on the I2C bus.
||Redundant data strobe (x8
devices only): RDQS is enabled/disabled via the LOAD MODE command to the
extended mode register (EMR). When RDQS is enabled, RDQS is output with read
data only and is ignored during write data. When RDQS is disabled, RDQS becomes
data mask (see DMx). RDQS# is only used when RDQS is enabled and differential
data strobe mode is enabled.
|Parity error output:
Parity error found on the command and address bus.
||Power supply: 1.8V
±0.1V. The component VDD and VDDQ are connected to
the module VDD.
||SPD EEPROM power
||No connect: These pins
are not connected on the module.
||No function: These pins
are connected within the module, but provide no functionality.
||Not used: These pins
are not used in specific module configurations/operations.
||Reserved for future use.