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Data Sheet Uploaded 08/2005

Parts associated with this datasheet:
MT9VDDT3272PHY-335 MT9VDDT6472PHY-335 MT9VDDT3272PHIY-335
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Features

Features


  • 200-pin, small-outline, dual in-line memory module (SODIMM)
  • Supports ECC error detection and correction
  • Fast data transfer rates: PC2100 and PC2700
  • Utilizes 266 MT/s and 333 MT/s DDR SDRAM components
  • 128MB (16 Meg x 72); 256MB (32 Meg x 72); 512MB (64 Meg x 72); 1GB (128 Meg x 72)
  • Vdd = VddQ = +2.5V
  • Vddspd = +2.3V to +3.6V
  • 2.5V I/O (SSTL_2 compatible)
  • Commands entered on each positive CK edge
  • DQS edge-aligned with data for READs; center-aligned with data for WRITEs
  • Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle
  • Four internal device banks for concurrent operation
  • Programmable burst lengths: 2, 4, or 8
  • Auto precharge option
  • Auto Refresh and Self Refresh Modes
  • 15.625µs (128MB), 7.8125µs (256MB, 512MB, 1GB) maximum average periodic refresh interval
  • Serial Presence Detect (SPD) with EEPROM
  • Programmable READ CAS latency
  • Bidirectional data strobe (DQS) transmitted/re-ceived with data—i.e., source-synchronous data capture
  • Differential clock inputs CK and CK#
  • Gold edge contacts
    Figure 1. 200-Pin SODIMM (MO-224)

Options Marking

Operating Temperature Range

Commercial (0°C ≤ TA ≤ +70°C)

None

Industrial (-40°C ≤ TA ≤ +85°C)

I1

Package

 

200-pin SODIMM (standard)

G

200-pin SODIMM (lead-free)

Y1

Memory Clock, Speed, CAS Latency2

 

6ns (267 MHz), 333 MT/s, CL = 2.5

-335

7.5ns (133 MHz), 266 MT/s, CL = 2

-2621

7.5ns (133 MHz), 266 MT/s, CL = 2

-26A1

7.5ns (133 MHz), 266 MT/s, CL = 2.5

-265

PCB Height

 

1.25in. (31.75mm)

Notes

  1. Consult Micron for product availability; industrial temperature option available in -265 speed only.

  2. CL = Device CAS (READ) Latency.

Table 1. Addressing
Parameter 128MB 256MB 512MB 1GB
Refresh count 4K 8K 8K 8K
Row address 4K (A0–A11) 8K (A0–A12) 8K (A0–A12) 16K (A0–A13)
Device bank address 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)
Device configuration 128Mb (16 Meg x 8) 256Mb (32 Meg x 8) 512Mb (64 Meg x 8) 1Gb (128 Meg x 8)
Column address 1K (A0–A9) 1K (A0–A9) 1K (A0–A9, A11) 2K (A0–A9, A11)
Module rank address 1 (S0#) 1 (S0#) 1 (S0# 1 (S0#)
Table 2. Part Numbers and Timing Parameters
Part Number
 Module Density Configuration Module
Bandwidth Memory Clock/
Data Rate Clock Latency
(CL - tRCD - tRP)
MT9VDDT1672PHG-335_ 128MB 16 Meg x 72 2.7 GB/s 6ns, 333 MT/s 2.5-3-3
MT9VDDT1672PHY-335_ 128MB 16 Meg x 72 2.7 GB/s 6ns, 333 MT/s 2.5-3-3
MT9VDDT1672PHG-262_ 128MB 16 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-2-2
MT9VDDT1672PHY-262_ 128MB 16 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-2-2
MT9VDDT1672PHG-26A_ 128MB 16 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-3-3
MT9VDDT1672PHY-26A_ 128MB 16 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-3-3
MT9VDDT1672PH(I)G-265_ 28MB 16 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2.5-3-3
MT9VDDT1672PH(I)Y-265_ 128MB 16 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2.5-3-3
MT9VDDT3272PHG-335_ 256MB 32 Meg x 72 2.7 GB/s 6ns, 333 MT/s 2.5-3-3
MT9VDDT3272PHY-335_ 256MB 32 Meg x 72 2.7 GB/s 6ns, 333 MT/s 2.5-3-3
MT9VDDT3272PHG-262_ 256MB 32 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-2-2
MT9VDDT3272PHY-262_ 256MB 32 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-2-2
MT9VDDT3272PHG-26A_ 256MB 32 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-3-3
MT9VDDT3272PHY-26A_ 256MB 32 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-3-3
MT9VDDT3272PH(I)G-265_ 256MB 32 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2.5-3-3
MT9VDDT3272PH(I)Y-265_ 256MB 32 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2.5-3-3
MT9VDDT6472PHG-335_ 512MB 64 Meg x 72 2.7 GB/s 6ns, 333 MT/s 2.5-3-3
MT9VDDT6472PHY-335_ 512MB 64 Meg x 72 2.7 GB/s 6ns, 333 MT/s 2.5-3-3
MT9VDDT6472PHG-262_ 512MB 64 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-2-2
MT9VDDT6472PHY-262_ 512MB 64 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-2-2
MT9VDDT6472PHG-26A_ 512MB 64 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-3-3
MT9VDDT6472PHY-26A_ 512MB 64 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-3-3
MT9VDDT6472PH(I)G-265_ 512MB 64 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2.5-3-3
MT9VDDT6472PH(I)Y-265_ 512MB 64 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2.5-3-3
MT9VDDT12872PHG-335_ 1GB 128 Meg x 72 2.7 GB/s 6ns, 333 MT/s 2.5-3-3
MT9VDDT12872PHY-335_ 1GB 128 Meg x 72 2.7 GB/s 6ns, 333 MT/s 2.5-3-3
MT9VDDT12872PHG-262_ 1GB 128 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-2-2
MT9VDDT12872PHY-262_ 1GB 128 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-2-2
MT9VDDT12872PHG-26A_ 1GB 128 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-3-3
MT9VDDT12872PHY-26A_ 1GB 128 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2-3-3
MT9VDDT12872PH(I)G-265_ 1GB 128 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2.5-3-3
MT9VDDT12872PH(I)Y-265_ 1GB 128 Meg x 72 2.1 GB/s 7.5ns, 266 MT/s 2.5-3-3

All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT9VDDT3272PHG-265A1.

UNKNOWN

Pin Assignments and Descriptions

Pin Assignments and Descriptions

Table 1. Pin Assignment

200-Pin SODIMM Front 200-Pin SODIMM Back
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1 Vref 51 Vss 101 A9 151 DQ42 2 Vref 52 Vss 102 A8 152 DQ46
3 Vss 53 DQ19 103 Vss 153 DQ43 4 Vss 54 DQ23 104 Vss 154 DQ47
5 DQ0 55 DQ24 105 A7 155 Vdd 6 DQ4 56 DQ28 106 A6 156 Vdd
7 DQ1 57 Vdd 107 A5 157 Vdd 8 DQ5 58 Vdd 108 A4 158 NC
9 Vdd 59 DQ25 109 A3 159 Vss 10 Vdd 60 DQ29 110 A2 160 NC
11 DQS0 61 DQS3 111 A1 161 Vss 12 DM0 62 DM3 112 A0 162 Vss
13 DQ2 63 Vss 113 Vdd 163 DQ48 14 DQ6 64 Vss 114 Vdd 164 DQ52
15 Vss 65 DQ26 115 A10/AP 165 DQ49 16 Vss 66 DQ30 116 BA1 166 DQ53
17 DQ3 67 DQ27 117 BA0 167 Vdd 18 DQ7 68 DQ31 118 RAS# 168 Vdd
19 DQ8 69 Vdd 119 WE# 169 DQS6 20 DQ12 70 Vdd 120 CAS# 170 DM6
21 Vdd 71 CB0 121 S0# 171 DQ50 22 Vdd 72 CB4 122 NC 172 DQ54
23 DQ9 73 CB1 123 NC/A13 173 Vss 24 DQ13 74 CB5 124 NC 174 Vss
25 DQS1 75 Vss 125 Vss 175 DQ51 26 DM1 76 Vss 126 Vss 176 DQ55
27 Vss 77 DQS8 127 DQ32 177 DQ56 28 Vss 78 DM8 128 DQ36 178 DQ60
29 DQ10 79 CB2 129 DQ33 179 Vdd 30 DQ14 80 CB6 130 DQ37 180 Vdd
31 DQ11 81 Vdd 131 Vdd 181 DQ57 32 DQ15 82 Vdd 132 Vdd 182 DQ61
33 Vdd 83 CB3 133 DQS4 183 DQS7 34 Vdd 84 CB7 134 DM4 184 DM7
35 CK0 85 NC 135 DQ34 185 Vss 36 Vdd 86 NC 136 DQ38 186 Vss
37 CK0# 87 Vss 137 Vss 187 DQ58 38 Vss 88 Vss 138 Vss 188 DQ62
39 Vss 89 NC 139 DQ35 189 DQ59 40 Vss 90 Vss 140 DQ39 190 DQ63
41 DQ16 91 NC 141 DQ40 191 Vdd 42 DQ20 92 Vdd 142 DQ44 192 Vdd
43 DQ17 93 Vdd 143 Vdd 193 SDA 44 DQ21 94 Vdd 144 Vdd 194 SA0
45 Vdd 95 NC 145 DQ41 195 SCL 46 Vdd 96 CKE0 146 DQ45 196 SA1
47 DQS2 97 NC 147 DQS5 197 Vddspd 48 DM2 98 NC 148 DM5 198 SA2
49 DQ18 99 NC/A12 149 Vss 199 NC 50 DQ22 100 A11 150 Vss 200 NC

Notes

  1. Pin 99 is a No Connect (NC) for 128MB; A12 for 256MB, 512MB, and 1GB.

  2. Pin 123 is a No Connect (NC) for 128MB, 256MB, and 512MB; A13 for 1GB

Figure 1. Module Layout


Table 2. Pin Descriptions

Refer to Pin Assignment Tables on Pin Assignment for pin number and symbol correlation.

Pin Numbers Symbol Type Description
118, 119, 120 WE#, CAS#, RAS# Input Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered.
35, 37 CK0, CK0# Input Clock: CK and CK# are differential clock inputs distributed through an on-board PLL to all devices. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQ and DQS) is referenced to the crossings of CK and CK#.
96 CKE0, Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers.and output drivers. Taking CKE LOW provides PRECHARGE POWER- DOWN and SELF REFRESH operations (all device banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any device bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWER-DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after Vdd is applied.
121 S0# Input Chip Select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All com- mands are masked when S# is registered HIGH. S# is considered part of the command code.
117, 116 BA0, BA1 Input Bank Address: BA0, BA1 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied.
99 (A12), 100, 101,102, 105, 106, 107, 108, 109, 110, 111, 112, 115,
123 (A13) A0–A11
(128MB)
A0–A12
(256MB, 512MB)
A0–A13
(1GB) Input Address Inputs: A0-A11/A12 provide the row address for ACTIVE commands, and the column address, and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command.
11, 25, 47, 61, 77, 133, 147,169, 183 DQS0–DQS8 Input/
Output Data Strobe: Output with READ data, input with WRITE data. DQS is edge-aligned with READ data, centered in WRITE data. Used to capture data.
12, 26, 48, 62, 78, 134, 148, 170, 184 DM0–DM8 Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins.
71, 72, 73, 74, 79, 80, 83, 84 CB0–CB7 Input/
Output Check Bits.
5, 6, 7, 8, 13, 14, 17, 18, 19, 20, 23, 24, 29, 30, 31, 32, 41, 42, 43, 44, 49, 50, 53, 54, 55, 56, 59, 60, 61, 65, 66, 67, 68, 127, 128, 129, 130, 135, 136, 139, 140, 141, 142, 145, 146, 151, 152, 153, 154, 163, 164, 165, 166, 171, 172, 175, 176, 177, 181, 182, 187, 188, 189, 190 DQ0–DQ63 Input/ Output Data I/Os: Data bus.
195 SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module.
194, 196, 198 SA0–SA2 Input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device.
193 SDA Input/
Output Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module.
1, 2 Vref Supply SSTL_2 reference voltage.
9, 10, 21, 22, 33, 34, 36, 45, 46, 57, 58, 69, 70, 81, 82, 92, 93, 94, 113, 114, 131, 132, 143, 144, 155, 156, 157, 167, 168, 179, 180, 191, 192 Vdd Supply DQ Power Supply: +2.5V ±0.2V.
3, 4, 15, 16, 27, 28, 38, 39, 40, 51, 52, 63, 64, 75, 76, 87, 88, 90, 103, 104, 125, 126, 137, 138, 149, 150, 159, 161, 162, 173, 174, 185, 186 Vss Supply Ground.
197 Vddspd Supply Serial EEPROM positive power supply: +2.3V to +3.6V.
85, 86, 89, 91, 95, 97, 98,
99 (128MB), 122, 123 (128MB, 256MB, 512MB), 124, 158, 160, 200 NC No Connect: These pins should be left unconnected.
UNKNOWN

Functional Block Diagram

Functional Block Diagram

All resistor values are 22Ω unless otherwise specified. Per industry standard, Micron modules utilize various component speed grades, as referenced in the module part numbering guide at www.micron.com/numberguide.

Standard modules use the following DDR SDRAM devices: MT46V16M8TG (128MB); MT46V32M8TG (256MB); MT46V64M8TG (512MB); and MT46V128M8TG (1GB).

Lead-free modules use the following DDR SDRAM devices: MT46V16M8P (128MB); MT46V32M8P (256MB); MT46V64M8P (512MB); and MT46V128M8P (1GB). Contact Micron for information on IT modules.

Figure 1. Functional Block Diagram


UNKNOWN