logo-micron

Add Bookmark(s)


To:

Email


Bookmark(s) shared successfully!

Please provide at least one email address.

Data Sheet Uploaded 01/2014

Features

Features


  • VDD/VDDQ = 1.70–1.95V

  • Bidirectional data strobe per byte of data (DQS)

  • Internal, pipelined double data rate (DDR)
    architecture; two data accesses per clock cycle

  • Differential clock inputs (CK and CK#)

  • Commands entered on each positive CK edge

  • DQS edge-aligned with data for READs; center-aligned with data for WRITEs

  • 4 internal banks for concurrent operation

  • Data masks (DM) for masking write data; one mask per byte

  • Programmable burst lengths (BL): 2, 4, 8, or 16

  • Concurrent auto precharge option is supported

  • Auto refresh and self refresh modes

  • 1.8V LVCMOS-compatible inputs

  • Temperature-compensated self refresh (TCSR)

  • Partial-array self refresh (PASR)

  • Deep power-down (DPD)

  • Status read register (SRR)

  • Selectable output drive strength (DS)

  • Clock stop capability

  • 64ms refresh, 32ms for automotive temperature

    Table 1. Key Timing Parameters (CL = 3)
    Speed Grade Clock Rate Access Time
    -5 200 MHz 5.0ns
    -54 185 MHz 5.0ns
    -6 166 MHz 5.0ns
    -75 133 MHz 6.0ns

    Options Marking

    VDD/VDDQ

    1.8V/1.8V

    H

    Configuration

    64 Meg x 16 (16 Meg x 16 x 4 banks)

    64M16

    32 Meg x 32 (8 Meg x 32 x 4 banks)

    32M32

    Addressing

    JEDEC-standard

    LF

    Plastic "green" package

    60-ball VFBGA (8mm x 9mm)1

    BF

    90-ball VFBGA (8mm x 13mm)2

    B5

    PoP (plastic "green" package)

     

    168-ball WFBGA (12mm x 12mm)2

    MA

    Timing – cycle time

    5ns @ CL = 3 (200 MHz)

    -5

    5.4ns @ CL = 3 (185 MHz)

    -54

    6ns @ CL = 3 (166 MHz)

    -6

    7.5ns @ CL = 3 (133 MHz)

    -75

    Power

    Standard IDD2/IDD6

    None

    Operating temperature range

    Commercial (0˚ to +70˚C)

    None

    Industrial (–40˚C to +85˚C)

    IT

    Automotive (–40˚C to +105˚C)3

    AT

    Design revision

    :B

    Notes

    1. Only available for x16 configuration.

    2. Only available for x32 configuration.

    3. Contact factory for availability.

Table 2. Configuration Addressing
Architecture 64 Meg x 16 32 Meg x 32
Configuration 16 Meg x 16 x 4 banks 8 Meg x 32 x 4 banks
Refresh count 8K 8K
Row addressing 16K A[13:0] 8K A[12:0]
Column addressing 1K A[9:0] 1K A[9:0]
Figure 1. 1Gb Mobile LPDDR Part Numbering


FBGA Part Marking Decoder

Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Micron’s FBGA part marking decoder is available at www.micron.com/decoder .

Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

General Description

General Description

The 1Gb Mobile low-power DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824 bits. It is internally configured as a quad-bank DRAM. Each of the x16’s 268,435,456-bit banks is organized as 16,384 rows by 1024 columns by 16 bits. Each of the x32’s 268,435,456-bit banks is organized as 8192 rows by 1024 columns by 32 bits.

Note:

1. Throughout this data sheet, various figures and text refer to DQs as “DQ.” DQ should be interpreted as any and all DQ collectively, unless specifically stated otherwise. Additionally, the x16 is divided into 2 bytes: the lower byte and the upper byte. For the lower byte (DQ[7:0]), DM refers to LDM and DQS refers to LDQS. For the upper byte (DQ[15:8]), DM refers to UDM and DQS refers to UDQS. The x32 is divided into 4 bytes. For DQ[7:0], DM refers to DM0 and DQS refers to DQS0. For DQ[15:8], DM refers to DM1 and DQS refers to DQS1. For DQ[23:16], DM refers to DM2 and DQS refers to DQS2. For DQ[31:24], DM refers to DM3 and DQS refers to DQS3.

2. Complete functionality is described throughout the document; any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements.

3. Any specific requirement takes precedence over a general statement.

Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

Functional Block Diagrams

Functional Block Diagrams

Figure 1. Functional Block Diagram (x16)


Figure 2. Functional Block Diagram (x32)


Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.