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MT48LC4M16A2P-7E

Data Sheets (1)

Data Sheet
  • File Type: PDF
  • Updated: 05/2015

Specs

Orderable Parts for: MT48LC4M16A2P-7E
Status Media FBGA Code SPD Data Chipset
Validation
PLP Start Date Alternative Part
MT48LC4M16A2P-7E:J Production N/A N/A N/A N/A No N/A
Detailed Specifications
Density 64Mb Part Status Production RoHS Yes Depth 4Mb
Width x16 Voltage 3.3V Package TSOP Pin Count 54-pin
Clock Rate 133 MHz Cycle Time 7.5ns Op. Temp. 0C to +70C CL CL = 2
Data Rate PC133

Sim Models & Software

Sim Models
HSpice
HSpice (ZIP)

2.0 (Die Rev. J)

  • File Type: ZIP
  • Updated: 09/29/2011
IBIS
IBIS (ZIP)

2.0 (Die Rev. J)

  • File Type: ZIP
  • Updated: 09/29/2011
HSpice
HSpice (ZIP)

2.1

  • File Type: ZIP
  • Updated: 06/24/2008
IBIS
IBIS (ZIP)

2.2

  • File Type: ZIP
  • Updated: 06/24/2008
Verilog
Verilog (ZIP)

  • File Type: ZIP
  • Updated: 10/03/2001

RoHS Certificates

RoHS Certificates
RoHS Certificate of Compliance (PDF)

Part-specific certification of how this product meets the requirements of the current DIRECTIVE 2002/95/EC, a.k.a. Restriction of Hazardous Substances (RoHS) Directive.

  • File Type: (PDF)
  • Updated: 12/2016
RoHS Certificates
China RoHS Certificate (PDF)

Part-specific certification as required by China's Management Methods for Controlling Pollution by Electronic Information Products.

  • File Type: (PDF)
  • Updated: 12/2016

Documentation & Support

See All SDRAM Documentation
Technical Notes
Search (7) SDRAM Technical Notes
Technical Notes


(TN-00-01) This technical note describes shipping procedures for preventing memory devices from absorbing moisture and recommendations for baking devices exposed to excessive moisture.

  • File Type: PDF
  • Updated: 02/14/2013
Technical Notes


(TN-00-24) This technical note compares the I/O characteristics of the 54nm to the 130nm single data rate (SDR) synchronous dynamic random access memory (SDRAM) die.

  • File Type: PDF
  • Updated: 05/25/2011
Technical Notes


(TN-48-09) Describes the proper setup and hold time derating when the slew rate during transition time violates specification.

  • File Type: PDF
  • Updated: 11/19/2009
Technical Notes


(TN-00-19) This technical note provides information on optimal wafer-thinning processes to meet specific customer requirements.

  • File Type: PDF
  • Updated: 10/15/2009
Technical Notes


(TN-46-14) This technical note provides hardware tips for point-to-point system design including termination, layout, and routing.

  • File Type: PDF
  • Updated: 06/30/2008
Search (7) SDRAM Technical Notes

Parts with the same Data Sheet (9)

MT48LC4M16A2P-7E ( Current ) MT48LC4M16A2P-7E IT MT48LC4M16A2TG-7E IT MT48LC8M8A2TG-75 IT MT48LC4M16A2B4-6A IT MT48LC4M16A2P-6A IT MT48LC4M16A2P-6A MT48LC4M16A2TG-6A IT MT48LC4M16A2TG-6A MT48LC8M8A2P-6A
Part Status Production Production End of Life End of Life Production Production Production Obsolete End of Life Contact Factory
Density 64Mb 64Mb 64Mb 64Mb 64Mb 64Mb 64Mb 64Mb 64Mb 64Mb
RoHS Yes Yes 5/6 5/6 Yes Yes Yes 5/6 5/6 Yes
Depth 4Mb 4Mb 4Mb 8Mb 4Mb 4Mb 4Mb 4Mb 4Mb 8Mb
Width x16 x16 x16 x8 x16 x16 x16 x16 x16 x8
Voltage 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
Package TSOP TSOP TSOP TSOP VFBGA TSOP TSOP TSOP TSOP TSOP
Pin Count 54-pin 54-pin 54-pin 54-pin 54-ball 54-pin 54-pin 54-pin 54-pin 54-pin
Clock Rate 133 MHz 133 MHz 133 MHz 133 MHz 166 MHz 166 MHz 166 MHz 166 MHz 166 MHz 166 MHz
Cycle Time 7.5ns 7.5ns 7.5ns 7.5ns 6ns 6ns 6ns 6ns 6ns 6ns
Op. Temp. 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C 0C to +70C -40C to +85C 0C to +70C 0C to +70C
CL CL = 2 CL = 2 CL = 2 CL = 3 CL = 3 CL = 3 CL = 3 CL = 3 CL = 3 CL = 3
Data Rate PC133 PC133 PC133 PC133 PC133 PC133 PC133 PC133 PC133 PC133

Where to Buy

Orderable Parts
Status Media FBGA Code SPD Data Chipset
Validation
PLP Start Date Alternative Part
MT48LC4M16A2P-7E:J Production N/A N/A N/A N/A No N/A
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