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MT41K256M16TW-107 AUT

Data Sheets (1)

Data Sheet
MT41K512M8: 64 Meg x 8 x 8 banks; MT41K256M16: 32 Meg x 16 x 8 banks
  • File Type: PDF
  • Updated: 05/2016

Specs

Orderable Parts for: MT41K256M16TW-107 AUT
Status Media FBGA Code SPD Data Chipset
Validation
PLP Start Date Alternative Part
MT41K256M16TW-107 AUT:P Sampling N/A D9TRN N/A N/A No N/A
Detailed Specifications
Density 4Gb Part Status Sampling RoHS Yes Depth 256Mb
Width x16 Voltage 1.35V Package FBGA Pin Count 96-ball
Clock Rate 933 MHz Cycle Time 1.071ns Op. Temp. -40C to +125C CL CL = 13
Data Rate DDR3-1866 Features

Sim Models & Software

Sim Models
HSpice
HSpice (ZIP)

2.0 (Die Rev. P)

  • File Type: ZIP
  • Updated: 01/28/2016
IBIS
IBIS (ZIP)

2.0 (Die Rev.P)

  • File Type: ZIP
  • Updated: 01/28/2016

RoHS Certificates

RoHS Certificates
RoHS Certificate of Compliance (PDF)

Part-specific certification of how this product meets the requirements of the current DIRECTIVE 2002/95/EC, a.k.a. Restriction of Hazardous Substances (RoHS) Directive.

  • File Type: (PDF)
  • Updated: 12/2016
RoHS Certificates
China RoHS Certificate (PDF)

Part-specific certification as required by China's Management Methods for Controlling Pollution by Electronic Information Products.

  • File Type: (PDF)
  • Updated: 12/2016

Documentation & Support

See All DDR3 SDRAM Documentation
Technical Notes
Search (15) DDR3 SDRAM Technical Notes
Technical Notes


(TN-00-33) This technical note describes the new features in IBIS 5.0 enabling PI simulation. It also provides an overview of some of the modeling accuracy challenges and compares SSO simulation results using various electronic design automation (EDA) software tools.

  • File Type: PDF
  • Updated: 01/25/2016
Technical Notes


(E1503E10) This manual is intended for users who design application systems using DDR3 SDRAM manufactured by Elpida.

  • File Type: PDF
  • Updated: 02/26/2014
Technical Notes


(TN-41-16) This technical note explains how to transition a dual-rank 8Gb 2CS (dual die) MT41K512M16 DDP device to a single-rank 8Gb 1CS (monolithic) MT41K512M16 SDP device.

  • File Type: PDF
  • Updated: 02/12/2014
Technical Notes


(TN-41-13) DDR3 is an evolutionary transition from DDR2.

  • File Type: PDF
  • Updated: 08/02/2013
Technical Notes


(TN-41-15) Describes proper interpretation and use of VOL and VOH specifications.

  • File Type: PDF
  • Updated: 07/23/2013
Search (15) DDR3 SDRAM Technical Notes

Parts with the same Data Sheet (5)

MT41K256M16TW-107 AUT ( Current ) MT41K512M8DA-107 AIT MT41K256M16TW-107 AIT MT41K256M16TW-107 AAT MT41K512M8DA-107 AAT MT41K512M8DA-107 AIT
Part Status Sampling Production Production Production Production Production
Density 4Gb 4Gb 4Gb 4Gb 4Gb 4Gb
RoHS Yes Yes Yes Yes Yes Yes
Depth 256Mb 512Mb 256Mb 256Mb 512Mb 512Mb
Width x16 x8 x16 x16 x8 x8
Voltage 1.35V 1.35V 1.35V 1.35V 1.35V 1.35V
Package FBGA FBGA FBGA FBGA FBGA FBGA
Pin Count 96-ball 78-ball 96-ball 96-ball 78-ball 78-ball
Clock Rate 933 MHz 933 MHz 933 MHz 933 MHz 933 MHz 933 MHz
Cycle Time 1.071ns 1.071ns 1.071ns 1.071ns 1.071ns 1.071ns
Op. Temp. -40C to +125C -40C to +95C -40C to +95C -40C to +105C -40C to +105C -40C to +95C
CL CL = 13 CL = 13 CL = 13 CL = 13 CL = 13 CL = 13
Data Rate DDR3-1866 DDR3-1866 DDR3-1866 DDR3-1866 DDR3-1866 DDR3-1866
Features

Where to Buy

Orderable Parts
Status Media FBGA Code SPD Data Chipset
Validation
PLP Start Date Alternative Part
MT41K256M16TW-107 AUT:P Sampling N/A D9TRN N/A N/A No N/A
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