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MT41K128M16JT-125 AAT

Data Sheets (1)

Data Sheet
MT41K256M8 (32 Meg x 8 x 8 banks), MT41K128M16 (16 Meg x 16 x 8 banks)
  • File Type: PDF
  • Updated: 06/2016

Specs

Orderable Parts for: MT41K128M16JT-125 AAT
Status Media FBGA Code SPD Data Chipset
Validation
PLP Start Date Alternative Part
MT41K128M16JT-125 AAT:K Production N/A D9PTH N/A N/A Yes 05/04/2011 N/A
Detailed Specifications
Density 2Gb Part Status Production RoHS Yes Depth 128Mb
Width x16 Voltage 1.35V Package FBGA Pin Count 96-ball
Clock Rate 800 MHz Cycle Time 1.25ns Op. Temp. -40C to +105C CL CL = 11
Data Rate DDR3-1600 Features

Sim Models & Software

Sim Models
HSpice

Revision 2.2 (Die Rev. K)

  • File Type: ZIP
  • Updated: 07/28/2016
IBIS

Revision 2.2 (Die Rev. K)

  • File Type: ZIP
  • Updated: 07/28/2016

RoHS Certificates

RoHS Certificates
RoHS Certificate of Compliance (PDF)

Part-specific certification of how this product meets the requirements of the current DIRECTIVE 2002/95/EC, a.k.a. Restriction of Hazardous Substances (RoHS) Directive.

  • File Type: (PDF)
  • Updated: 12/2016
RoHS Certificates
China RoHS Certificate (PDF)

Part-specific certification as required by China's Management Methods for Controlling Pollution by Electronic Information Products.

  • File Type: (PDF)
  • Updated: 12/2016

Documentation & Support

See All DDR3 SDRAM Documentation
Technical Notes
Search (15) DDR3 SDRAM Technical Notes
Technical Notes


(TN-00-33) This technical note describes the new features in IBIS 5.0 enabling PI simulation. It also provides an overview of some of the modeling accuracy challenges and compares SSO simulation results using various electronic design automation (EDA) software tools.

  • File Type: PDF
  • Updated: 01/25/2016
Technical Notes


(E1503E10) This manual is intended for users who design application systems using DDR3 SDRAM manufactured by Elpida.

  • File Type: PDF
  • Updated: 02/26/2014
Technical Notes


(TN-41-16) This technical note explains how to transition a dual-rank 8Gb 2CS (dual die) MT41K512M16 DDP device to a single-rank 8Gb 1CS (monolithic) MT41K512M16 SDP device.

  • File Type: PDF
  • Updated: 02/12/2014
Technical Notes


(TN-41-13) DDR3 is an evolutionary transition from DDR2.

  • File Type: PDF
  • Updated: 08/02/2013
Technical Notes


(TN-41-15) Describes proper interpretation and use of VOL and VOH specifications.

  • File Type: PDF
  • Updated: 07/23/2013
Search (15) DDR3 SDRAM Technical Notes

Parts with the same Data Sheet (3)

MT41K128M16JT-125 AAT ( Current ) MT41K256M8DA-125 AAT MT41K256M8DA-125 AIT MT41K128M16JT-125 AIT
Part Status Production Production Production Production
Density 2Gb 2Gb 2Gb 2Gb
RoHS Yes Yes Yes Yes
Depth 128Mb 256Mb 256Mb 128Mb
Width x16 x8 x8 x16
Voltage 1.35V 1.35V 1.35V 1.35V
Package FBGA FBGA FBGA FBGA
Pin Count 96-ball 78-ball 78-ball 96-ball
Clock Rate 800 MHz 800 MHz 800 MHz 800 MHz
Cycle Time 1.25ns 1.25ns 1.25ns 1.25ns
Op. Temp. -40C to +105C -40C to +105C -40C to +95C -40C to +95C
CL CL = 11 CL = 11 CL = 11 CL = 11
Data Rate DDR3-1600 DDR3-1600 DDR3-1600 DDR3-1600
Features

Where to Buy

Orderable Parts
Status Media FBGA Code SPD Data Chipset
Validation
PLP Start Date Alternative Part
MT41K128M16JT-125 AAT:K Production N/A D9PTH N/A N/A Yes 05/04/2011 N/A
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