Brent Keeth

Senior Fellow, Advanced DRAM Architectures, DRAM Solutions Group

As a Senior Fellow in the Advanced DRAM Architecture Group in DSG, Brent Keeth directs ultrahigh performance memory design and technology development programs including the Hybrid Memory Cube (HMC). He identifies technical problem areas, design opportunities, and manufacturing issues and he investigates / develops candidate solutions to those issues with an emphasis on power, robustness, fault tolerance, and cost. He provides technical support to a variety of design efforts at Micron and helps Micron overcome barriers to efficient and successful product design by driving capability, infrastructure, methodology, and CAE improvements as needed. Brent also facilitates the development of Micron’s intellectual property assets in the ultrahigh performance memory space, supports strategic technology exploration of new product opportunities, and advances Micron’s stake & interests with a variety of external research organizations.

Brent received his BSEE & MSEE from the University of Idaho, Moscow in 1982 and 1996 and joined Micron in 1992. Brent's initial accomplishments include Micron's basic voltage regulator architecture, boosted ISO gate sense amplifier, and definition of the bi-level digit line architecture which was Micron's premier 6F2 architecture. Since 1996, Brent participated in the development of high speed memory interface standards. Brent and team have been responsible for first generation high performance DRAMs and have contributed significantly to Micron’s high speed design knowledge. Many of the circuits, architectures, and techniques developed can be found in Micron’s DDR, DDR2 and DDR3 designs. Furthermore, Brent pushed for the development of new tools needed to validate the performance and accuracy of high-speed designs.

Brent has served on Program Committees for the VLSI Symposium and ISSCC, and was as an invited panelist on low power/voltage design and VLSI interconnect issues at the VLSI Symposium. Brent has given lectures on redundancy at the VLSI Symposium, clock domain crossing at the University of Idaho, and Advanced DRAM Technology to patent examiners at the U.S.P.T.O. He has also served on various University of Idaho engineering boards and committees. Brent co-authored the textbooks "DRAM Circuit Design: A Tutorial" and "DRAM Circuit Design: Fundamental and High-Speed Topics."