The video captures below correspond with and expand on Figures 6–12 in Micron’s technical paper entitled, An Efficient and Scalable Semiconductor Architecture for Parallel Automata Processing, which will appear in IEEE Transactions on Parallel and Distributed Systems.
The video captures are simulations from runs of the Micron AP Workbench, a visual editor for creating, visualizing, and simulating Automata, which is compatible with Micron’s Automata Processor. The video captures are in mp4 format, which should work in most viewers, such as Windows Media Player, and on any platform.
Figure 6: Counter Element Example
Implementation of a bounded sequence of numeric digits using Automata Processor counters. The simulation reports a match after 500 digits, followed by a # terminator; it shows a non-match when a subsequent sequence exceeds the maximum bound of 999 digits.
Figure 7: Pruning With Counters Example
Implementation of a cycle which is pruned after being traversed once. The simulation shows the three state transition elements and counter being traversed once on arbitrary input data and then being blocked from repeating as data continues to be input to the machine as a result of the counter having counted to its target of 1 on the first pass.
Figure 8: Boolean Element Example
Implementation of tests for the AND of two conditions that may occur at different points in the input sequence but are reported simultaneously at the end of data using the synchronous enable signal.
Figure 9: Snort PCRE Rule as Automata
Implementation of the equivalent Automata to a regular expression from Snort. The target sequence occurs in the input stream and is reported.
Figure 10: ANML Pattern Match Example
Implementation of Automata which reports on matching a sequence containing one or more symbols a, followed by one or more symbols b, followed by one or more symbols c; where the symbols a, b, and c total 17. The sequence is detected in the input and reported.
Figure 11: ANML Graph Example
Implementation of a breadth-first-search tree. The tree is composed of macro nodes containing keys. This simulation shows the tree only from the macro level, showing parallel descent of the tree, level by level on every four input symbol cycles, and coloring of the macro nodes. The simulation shows a matching node is identified on the third level.
Figures 11 and 12: ANML Graph Showing Internal Nodes
Implementation of a breadth-first-search tree with node details shown. Single stepping through the input, one more node is opened from the tree view so that the search for the key within the node is shown. On the third level of the tree, two nodes are opening, one showing the key not found and the other showing it found and reported.