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Come see Micron at The Linley Group Processor Conference
Oct. 4-5

Come see Micron at The Linley Group Processor Conference

Linley Processor ConferenceJoin us to discover the latest update regarding high performance memory products!

Graphics memory presents the most compelling cost-to-performance memory solution to address the aggressive bandwidth requirements of high-end networking applications. The upcoming release of the JEDEC GDDR6 memory standard builds on the proven success of prior generations, providing a path toward a remarkable 1 terabyte of system memory bandwidth.

In this talk, the Micron team will discuss real-world networking applications leveraging the system-level benefits of GDDR, and how this latest high-performance graphics memory standard sets a clear course for system designers to significantly increase bandwidth to address the increasing demands of next-generation platforms. 

Explore Micron's networking innovations.

About Our Blogger

Jay Walstrum

Jay Walstrum is a Senior System Architect for Micron’s Compute and Networking Business Unit, where he is focusing on new opportunities in the three to five-plus year timeframe. In his role, he also applies innovative technologies and memory architectures to solve customer system-level challenges.

Jay’s responsibilities include working closely with a market-strategy team to identify new technology, applications, product/architecture specifications, customers, and markets for new product concepts. He also actively works with customer system architects, technologists, third-party developers, and Micron’s Research and Development team to identify, define, and architect innovative memory solutions.

Before beginning with Micron in January 2013, Jay spent 22 years at Xilinx Corp, where he held various positions ranging from the Director of Quality, to the Senior Product Planning Manager, to the Strategic and Technical Marketing Leader.

Jay holds a BSEE from University of Southern California. He holds 11 patents in the areas of FPGA system Solutions and memory interface architecture.

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