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MCP 101

MCP 101

MCPs or Multichip Packages as they are commonly referred to in the memory industry, are single packages with multiple memory devices inside.  While the traditional definition of an MCP could include packages with multiple die of the same technology (like DRAM, NOR or NAND), typically used to attain higher densities, the definition has expanded to include packages that combine different technologies (like LPDRAM and NOR, or LPDRAM and NAND or LPDRAM) in a single package.  MCPs are generally offered in PoP (Package on Package) which are soldered directly on top of the processor and BGA (Ball Grid Array) packages which are soldered directly onto the Printed Circuit Board (PCB).

Traditional MCPs include a form of low-power DRAM (LPDRAM) like LPDDR2, and a form of Flash like NOR or NAND. There is a newer type of MCP called eMCP (e.MMC based MCP) which still includes LPDRAM but in place of NOR or NAND, it includes an e.MMC which has a controller managing the Flash so it looks more like a small Solid State Drive (SSD).  Since the eMCP products include a controller, they can often yield a simpler design, and are easier to migrate to larger densities or to newer devices for improved product longevity.

MCPs offer several obvious advantages to a design such as saving product space and weight, as well as less components to inventory.  MCPs can also improve the Signal Integrity (SI) of a design, by allowing a single, typically smaller package, to be placed closer to the processor or controller, meaning shorter PCB routing.  Improved SI can often allow one to achieve higher clock rates or provide additional design margin or noise immunity.

MCP’s shown as BGA and PoP packaging
Image 1: MCPs shown as BGA and PoP packaging

POP

PoP (Package on Package) devices are actually MCPs that are offered in a slightly different package.  The PoP is designed to mount on top of the processor as shown in Figure 1 and include only a few rows of perimeter balls.  While the main benefit of a PoP is the space savings, a PoP can be mounted on a PCB, which can sometimes simplify the PCB routing.

Pop packaging
Image 2:  Pop packaging

Pop package
Figure 1

Depending on the actual design, some board designers are able to reduce the number of PCB layers to route all the connections.  

In a recent wearable design, a designer estimated that the PCB design would have taken 10 layers using a MCP alongside of the processor.  Using a PoP, he estimated that the layer count could have been reduced from 10 down to 6 which can lead to a less expensive PCB.  In addition, a design that uses PoP memory is usually able to achieve even higher speeds than its MCP equivalent, which is often higher than a discrete implementation. As seen in Figure 2, this is due to the improved SI of the much shorter signals.  In addition, using a PoP reduces the X-Y footprint although it does impact the Z height.

As with the eMCP, ePoPs are also offered with LPDRAM and e.MMC.

MCP 101 Figure 2
Figure 2

MCP’s unique memory configurations with the right mixture of density, power, size, performance, temperature, reliability, cost, and support are making them a good fit for the many new and next generation IoT applications.  To find out more about Micron’s MCP offerings, see below for other related information:

Comments

  • JAMES MALATESTA on June 28, 2016

    Another advantage of PNOR + PSRAM MCP's is that they're lower density (32Mb-512Mb PNOR + 16Mb-128Mb PSRAM), high performance synchronous burst and share the same bus and many control signals, further reducing the signal count and package size - these were the MCP's that rendered in the generation of the cell phone as they were designed for mobile, low power 1.8V, small form factor applications.

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