Folks familiar with technology development know that by the time a working group or a company starts talking publicly about an innovation, it’s really just the tip of the iceberg of what may have been years of thought, problem solving, and development of a solution. All of this forward-looking momentum and investment is ultimately intended to solve problems. And the truth is that no one understands the shortcomings of a technology like the people who work in that technology every day—people like memory developers, chip designers, and system architects. These creative folks are also the ones who recognize roadblocks; they can then think differently and transform products to a level of performance that may not have been possible without collaborated innovation.
The Hybrid Memory Cube (HMC) is a groundbreaking technology developed through such collaboration. HMC is our response to system challenges around memory. It provides a simplified interface, unmatched performance, and the utmost reliability. It all starts with an abstracted memory interface that eliminates pages of complex DRAM timing. This means that you don’t have to be a DRAM expert to design in this memory. Because HMC supports up to 160 GB/s of sustained memory bandwidth, the most complex question becomes, “How fast do you want to run the interface?”
HMC accesses are made through high-speed serial buses that use the HMC Consortium (HMCC) protocol standard. Within this uncomplicated protocol, commands such as 128-byte WRITE (WR128), 64-byte READ (RD64), or dual 8-byte ADD IMMEDIATE (2ADD8) can be randomly mixed. Not only is the interface simplified, but the board layout is made easy too. Only a minimal number of signals are needed to route to and from the HMC device without stringent timing relationships between signals like data lines, strobe, and clock, as is typical for DDR channels. What a great concept. Why didn’t I think of that?
Of course, performance may have different criteria for each unique system design, but HMC addresses all aspects of performance without compromise. It performs reads and writes simultaneously and sequentially to any of the 16 autonomous DRAM vaults, which make up to 256 internal and unrestricted banks without any concern for tWR, tWTR, and tFAW timings. Scalable memory bandwidth is achieved by the optimization and configuration of one to four independent high-speed serial links. To promote even more flexibility, links can be set as “pass-through” links that allow one HMC to interface to multiple HMCs.
Another significant performance feature of the HMC device is the low energy per bit for its high-bandwidth memory access. HMC can complete transactions with typical energy values of 15−20 pJ/bit. Doing the math, a comparable DDR3- or DDR4-based system can easily consume in excess of 60−70 pJ/bit in attempt to keep pace. Features that are less obvious, but still important, include these heavy hitters: temperature-controlled and hidden refreshes that provide 3−6% performance improvement compared to traditional memory, embedded ATOMIC operations that can reduce external bus traffic, and sideband channels (JTAG or I2C) that enable device configuration and status monitoring without affecting in-band throughput.
With regard to reliability, it’s amazing how much system-level silicon is dedicated to correct and overcome the inherent and growing reliability problems within traditional DDR-based systems. In systems where data integrity is critical, CPUs have used sophisticated error-checking and redundancy schemes to patch together a system that would otherwise be inadequate for mission-critical applications. For example, refer to the Advanced Reliability for Intel® Xeon® Processor-Based Servers white paper.
HMC delivers maximum reliability with extremely simple and effective RAS features. Without going into all the gory detail, HMC supports vault-controller parity and ECC correction with data scrubbing that’s invisible to the user, self-correcting and in-system lifetime memory repair, extensive device health-monitoring capabilities, and real-time status reporting. HMC also features a highly reliable external serializer/deserializer (SERDES) interface with exceptional low-bit error rates (BER) that also support CRC and packet retry.
HMC promises flexible performance, concepts that are simple to design in, and reliability that was not previously possible. Bottom line—Micron’s Hybrid Memory Cube (HMC-15G-SR PHY) is here, and we’ve only begun to scratch the surface of its full capabilities. It’s exciting to be involved in a technology that has so much positive momentum and such a bright future. It really is worth talking about!
About Our Blogger
Tom Kinsley is a memory development engineer at Micron Technology. He is currently engaged in the development and enablement of the next-generation memory including Micron’s hybrid memory cube.
Mr. Kinsley joined Micron in 1988 and has held a variety of product design engineering roles. Some of his accomplishments in these roles include working on the development of IBM PC/AT and XT memory expansion cards, Apple Macintosh video cards and early memory modules SIMM (single in-line memory module).
Additionally, Mr. Kinsley holds more than 10 patents in the area of electronics engineering.