NAND Flash represents the most advanced semiconductor technology in the world, and is approaching the atomic level where storage cells are separated by a countable number of electrons. Taken at face value, one might assume that these advances are creating a palpable opportunity for designers to capitalize on increased market demands for higher density applications in consumer electronic devices, computing platforms, and industrial systems. However, there are a few hurdles that we need to overcome before customers can seize this burgeoning opportunity.
In traditional system architectures using NAND, the host controller assumes responsibility for all NAND management functions, including block management, wear leveling, and error correction code (ECC). In these instances, the host controller has to take into account the NAND ECC requirements for potentially multiple generations (process nodes) and multiple cell technologies (1/2/3 bits per cell), as well as the requirements from multiple suppliers.
Additionally, flash error management is rapidly moving beyond what today’s ECC schemes are capable of and in the near-future will require more advanced ECC and signal processing algorithms. On the other hand, the other NAND management functions are almost solely dependent on the application, something the host controller and system manufacturers are best suited to develop.
The solution? Let the NAND manufacturers worry about the flash error management. As a founding member of the ONFI Working Group, Micron has teaming up with other NAND Flash companies to create standards to ensure our customers can take advantage of the great strides we’re making in NAND flash without having to worry about the error management requirements. One of these standards is the EZ-NAND protocol, or ECC Zero NAND. In essence, EZ-NAND alleviates the burden of the host controller to implement and keep pace with the fast changing ECC requirements that is circumstance of NAND flash process shrink.
Here’s a side-by-side comparison of a traditional NAND architecture compared to the EZ-NAND architecture:
|Scaling complexity due to ECC and controller sizing issues
||Abstracted storage for better error management and more scalable capacity
|Increased requirements, both signal processing and ECC, cause controller implementations to be more tied to NAND Flash
||Minimized controller cost by combining with high bus speeds and increasing capacity and performance per pin on the controller
|Signal management is no longer contained at the interface boundary
||Less burden on host controller to keep up with fast changing ECC requirements
For more, drop me a question in the comments section and I’ll be in touch.
About Our Blogger
Kevin is Micron Technology's Director of NAND Marketing.