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Micron Blog

Setting the NAND Speed Record: Optimization Blows Away the Bottleneck

  • December 15, 2008
High Speed NAND, ONFI 2.0 and our PCI-e Demo Wow--there's a been a lot of buzz about our recent PCI-e demonstration so I thought I'd take a minute and talk a little about the NAND we use, as it illustrates how NAND flash, managed to run at its optimum performance, can deliver incredible performance to apps like these. So--our demo device utilizes NAND that’s based on standard SLC (Single Level Cell) NAND which has 100K write/erase cycles. However, we've optimized the flash component to be a Micron High Speed NAND. To clarify the difference: ONFI 2.0 is a shared specification and definition of a revolutionary new NAND interface. What High Speed NAND does is it builds upon the 2.0 interface to help achieve the performance shown. To back up a bit: the data transfer performance is based on two factors: Array Performance and Memory Bus Performance. The ONFI 2.0 interface resolves the Memory Bus bottleneck by increasing bandwidth from 40MB/S to 200MB/S. However, the array still limits the write performance. So High Speed NAND has been optimized to improve the array write performance by up to 30%. In combination, data can be read and written much faster than ever before. Prior to ONFI 2.0, customers resolved the transfer issue by either utilizing more channels so data can be transferred at the same time to multiple devices or using multiple devices chained together under same channel so one component can be read, while another can be written. And sometimes they even utilize both more channels and more devices. That's a lot of work. And the fact is, these work-arounds add to design complexity and cost. But by Using ONFI 2.0, you can reach much faster read performance because the path (bus) to and from the flash component has widened significantly. Of course, write performance will only see a slight increase because the array inside the device has not changed. Enter High Speed NAND. It solves the latter problem by introducing a new NAND array that resolves the write bottleneck. In the end ONFI 2.0 or High Speed NAND gets you to your performance targets without tons of added cost and/or complexity. Imagine if you will: So put it another (non-technical) way, imagine that your car is Data, the city streets are the NAND Array, and the interstate is your Bus Interface. (I do this all the time on my commute) ONFI 2.0 is similar to navigating your car through the city, but only finding relief to the congestion as you reach a wider and faster highway. Now, High Speed NAND (based on ONFI 2.0), is similar to navigating your car through a city with much wider streets and higher speed limits. Ultimately it means that more people can reach their out-of-state friends and relatives faster for the holidays. So, there you go. Let me know what you think--I hope this answers some of your NAND questions about what's under-the-NAND-hood that let's us achieve that amazing performance.
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