Memory technology is evolving at a rapid pace, and Micron’s DRAM and other memory products are now using speeds that make it challenging for engineers to test the robustness of their memory subsystems with traditional techniques. Knowing the timing margins on signals between the controller and the memory device is critical during qualifying to ensure high reliability in large-scale manufacturing.

What is the problem?

To assess the timing margins, the system designer needs to monitor the signal path over multiple read/write cycles to build a picture of the “data eye” for each signal of the DRAM or other memory interface.

Traditional methods, called physical timing and signal analysis (pTSA), involving removal of the memory device to insert an interposer connected to a scope via a series of test probes, are introducing parasitic inductance/capacitance effects that create “observer effects.” These observer effects can render the resulting traces unhelpful. Adding to the challenges, the interposer boards required are themselves becoming harder to design and more expensive.

It is also increasingly difficult to capture the information for plotting meaningful data eyes, even when using top-of-the-range $500,000 oscilloscopes.

No Oscilloscope Required

For timing and signal analysis — the art of making sure memory soldered to a printed circuit board is functioning correctly and reliably — you need a lab full of instruments, skill with a soldering iron and lots of time. Or do you?

Visit the blog and watch the video with Bill Filipiak and Rebecca Lewington.

In addition, manually reworking printed circuit boards (PCBs) to remove delicate components, attaching interposers, resoldering to the PCB, and attaching probes can damage the hardware under test. All these issues make it impractical to assess the signal integrity on anything more than just a couple of selected signals.

But there is a better way!

A radical new approach called vTSA (virtual timing and signal analysis) removes the need for any external probing or testing hardware. With vTSA, the system validates its own timing margins and provides a full picture of the timing margins across the memory interface.

Most modern memory controllers can already shift timing strobes and alter voltage references to “train” the controller to identify optimum memory interface settings during the initialization phase. vTSA takes advantage of this process by capturing the full training data for each signal and allowing it to be exported, typically via a serial port, for parsing into full 2D data eyes.

Example of a 2D data eye graphing results of signal tests on a memory device

The process is highly automated as this data capture is fully handled by the controller and requires no testing equipment on the memory interface. We can capture a complete set of data eyes for all signals in a matter of minutes, rather than the days it takes for pTSA. In addition, we mitigate any observer effects caused by the attachment of probes. Plus, there are no longer risks associated with manual removal of components and insertion of interposers.

The vTSA data recorded is more accurate, more comprehensive and more time and cost efficient. This approach also provides board designers with the TSA data they need to ensure their high-speed memory subsystems are robust.

Micron is working with chipset vendors to build vTSA capabilities into their future projects.

Learn more

For more information, watch this video podcast of “No Oscilloscope Required“ and read our white paper, Discover Your Memory System’s Signaling Margin Without Test Equipment. If you’re a board designer or system architect and want to find vTSA-aligned ecosystem connections for your future products, or you are a chipset/memory controller vendor and want to help your customers to achieve more robust systems, email us at vtsa@micron.com.