Artificial intelligence based on deep neural networks (DNNs) is transforming the automotive market in areas that include vision, voice and gesture recognition, sensor fusion, object recognition, human machine interface (HMI) and autonomous driving. Supporting highly complex DNNs in these silicon devices can easily require more than 10s of aggregate teraflops of computational performance. Voice- and gesture-based HMIs can easily demand 100s of gigabytes per second (GB/s) of memory bandwidth, and Level 4 and beyond autonomous driving can easily require more than 1 terabyte per second (TB/s) of memory bandwidth.

The realization is that this level of compute performance requires commensurate low-latency, high-bandwidth memory to ensure processing pipelines do not stall and associated system-level throughput is maintained. Increasingly, OEMs and tier-1 companies are relying on graphical processing units (GPUs), field programmable gate arrays (FPGAs), and multifunction system-on-chips (SOCs) to implement DNNs.

For autonomous driving, the use of DNNs for object detection and classification dramatically increases the accuracy of the sensor data fusion, which is used in a vehicle’s perception, localization, planning, and trajectory. Perception addresses sensor fusion, object detection, classification, and object tracking. Localization employs map fusion, which relies on detecting landmarks in conjunction with GPS data. Path planning establishes the trajectory and behavior of the vehicle, requiring complex, compute-intensive algorithms to calculate in four dimensions — x, y, z and time — while also being able to identify free space (the path where a vehicle can escape in case of a potential accident). Path planning must also be able to predict how the environment may change to determine what potential evasive actions may need to be taken.

To address DNNs, three main types of system-level architectures, with their own pros and cons, are currently being adopted in autonomous vehicles:

• Distributed architecture–close to the sensor/at the edge processing; this architecture is easy to manage, but there are power and size constraints
• Hybrid architecture – aggregate smart sensors into central fusion ECU processing; this architecture is easy to manage and is scalable, but there can be edge power sensitivity
• Centralized – fully central compute processing; this architecture requires simple sensors, has the lowest cost and highest central compute power, but has very high-power requirements and thermal tradeoffs

For each architecture type, Micron’s broad portfolio of automotive-qualified DRAM enables an optimal memory solution that provides the right mix of memory bandwidth vs. cost and power. Micron’s most recent introduction to the automotive DRAM portfolio — automotive-qualified GDDR6 — leverages Micron’s extensive history and leadership in GDDR memory to bring the highest memory bandwidth to the automotive market. GDDR6 ushers in a new era of extreme performance for artificial intelligence and DNNs for the automotive market.

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