Memory // Events

Wrapping up Linley and What's Next

By Jay Walstrum - 10.9.17

Micron at the Linley Processor Conference

The Linley Processor Conference that wrapped up last week has historically has been around processor development, and this year's conference was the same but with a twist. Many of the processor developments were framed around, or had something to do with Machine Learning. IP vendor's presentations focused on machine learning. Processors had some message about machine learning or acceleration of workloads.

Micron at the Linley Processor Conference

Education on Alexnet, VGG16, Resnet and Yolo were interesting to learn and tied very well into the Micron demonstration on Wednesday evening. The Yolo image above is a recognition application running on an Nvidia GEForce 1080Ti graphics card which leverages the Micron GDDR5X devices. This was 11GBytes of capacity running 10-20 frames per second using the "YOLOv2 608x608" model, which created a great discussion point with many attendees of the conference. More importantly, it supported the message of proven technology leading continuing the high-performance memory roadmap, leading to our GDDR6N announcement.

Micron at the Linley Processor Conference

If you are interested in seeing more about what Micron is doing with Machine Learning, come see us at SC17 November 13-16 in Denver, where we will provide more demonstrations on active systems and memory requirements for machine learning applications.  

Jay Walstrum

Jay Walstrum

Jay Walstrum is a Senior System Architect for Micron’s Compute and Networking Business Unit, where he is focusing on new opportunities in the three to five-plus year timeframe. In his role, he also applies innovative technologies and memory architectures to solve customer system-level challenges.

Jay’s responsibilities include working closely with a market-strategy team to identify new technology, applications, product/architecture specifications, customers, and markets for new product concepts. He also actively works with customer system architects, technologists, third-party developers, and Micron’s Research and Development team to identify, define, and architect innovative memory solutions.

Before beginning with Micron in January 2013, Jay spent 22 years at Xilinx Corp, where he held various positions ranging from the Director of Quality, to the Senior Product Planning Manager, to the Strategic and Technical Marketing Leader.

Jay holds a BSEE from University of Southern California. He holds 11 patents in the areas of FPGA system Solutions and memory interface architecture.

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