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Memory // Events

Announcing GDDR6N

By Jay Walstrum - 2017-10-04

This week at the Linley Processor Conference Micron announced our new GDDR6N technology – the latest high-performance GDDR technology for networking. This follows our automotive announcement at Mobile World Congress Americas a few weeks ago.

GDDR6N announcement
Dr. Andreas Schlapka – Director of Marketing – Networking Segment

At Micron, we clearly recognize the value GDDR technologies bring to high-performance designs. Our market-leading GDDR5X technology dominates the performance graphics segment while our pioneering GDDR5N technology is enabling a new breed of switching solutions in the data center.

With our latest GDDR6N technology, Micron continues this tradition of innovation and performance, designed to exceed the rigorous demands high bandwidth networking solutions place on the memory subsystem.

We’re actively engaged with partners and customers to enable our GDDR6 and GDDR6N technologies beyond the traditional graphics markets. Stay tuned – partner announcements to follow.

Contact us today for more details on how our latest GDDR6N technology can help your designs succeed. And check out our white paper, Extending the Benefits of GDDR Beyond Graphics.

Jay Walstrum

Jay Walstrum

Jay Walstrum is a Senior System Architect for Micron’s Compute and Networking Business Unit, where he is focusing on new opportunities in the three to five-plus year timeframe. In his role, he also applies innovative technologies and memory architectures to solve customer system-level challenges.

Jay’s responsibilities include working closely with a market-strategy team to identify new technology, applications, product/architecture specifications, customers, and markets for new product concepts. He also actively works with customer system architects, technologists, third-party developers, and Micron’s Research and Development team to identify, define, and architect innovative memory solutions.

Before beginning with Micron in January 2013, Jay spent 22 years at Xilinx Corp, where he held various positions ranging from the Director of Quality, to the Senior Product Planning Manager, to the Strategic and Technical Marketing Leader.

Jay holds a BSEE from University of Southern California. He holds 11 patents in the areas of FPGA system Solutions and memory interface architecture.