The Evolution of Serial NOR Flash

By Sundar Ranganathan - 2016-03-28

The need for reprogrammable external memory has always existed and this hasn't changed with modern day computing. In years past, Parallel EEPROM used to be the non-volatile external storage solution of choice - primarily used to store boot code, program code, configuration and data storage. SRAM was used as an external storage solution to store working memory. This combination of EEPROM and SRAM was based on shared-bus architecture.

System improvements drove memory densities higher and since EEPROM (using a 2T cell) and SRAM (using a 6T cell) were expensive, the system costs went up. Then, along came the Flash technology offering lower costs (using 1T cell), and DRAM (using 1T, 1 Cap) replaced SRAM as a low cost, high density alternative solution to store the working memory.

Moving away from shared-bus architecture, independent buses (parallel interface) took hold to improve performance. This dramatically increased MCU pin counts. Over time, as memory speeds increased, the parallel interface transitioned into serial interface (low pin count).

With time, the Non-volatile data storage requirements increased and Serial NOR flash was released to address this need. Three NOR flash architectures were introduced over time:

  • Page Erase - allows small erase granularity (256 bytes), incorporates Page Buffers to allow single byte reprogram, providing further flexibility.
  • Sector Erase - the memory array is divided into 64KB sectors. With the need to erase an entire block before a program operation, this solution was suitable for bulk code storage but not for data storage.
  • Block Erase – the 4KB blocks can be individually erased; this is good enough for many applications in terms of data storage and also provides flexibility in code storage.

In 1999, applications were designed with Serial NOR flash as a single solution to store code and data. These devices were used for code shadowing as they were not fast enough for in-place code execution.  As applications increased in complexity and performance, so did the need for a faster flash. Boot times needed to be quicker and the need for more throughput from the Serial NOR flash increased. Serial NOR solutions evolved from Single I/O to Dual I/O and Quad I/O. XiP (Execute in Place) mode was introduced to reduce random read latency.

While Parallel NOR flash did offer higher bandwidth and faster access times, it was at the cost of more pins and larger board footprints. Twin Quad Serial I/O devices evolved to better match the Parallel NOR performance at a smaller foot print and lower pin counts. This is important as the devices today are designed to be smaller and faster.

Micron's latest Octal NOR offering - Xccela™ Flash surpasses all NOR flash devices by offering significantly higher bandwidth (400MB/s), lower Initial word access (85.5ns, 16-bit) and Subsequent word access (2.5ns, 16-bit) times.

The below graph summarizes the Serial NOR flash evolution:

Xccela Flash, is the next generation of Serial NOR with only 9-10 active interface pins offers an octal SPI interface running at clock speeds of 200MHz, supporting up to 400MB/s read throughput, 4KB block erase, advanced sector and block protection.

In conclusion, the Serial NOR flash makes it easy to design a wide variety of applications as it provides choices (architecture and I/O widths):

  • 256-byte Page Erase is ideal for data logs, frequently modified configuration data etc. and can also be used for code shadowing
  • 64KB Sector Erase is ideal for bulk code shadowing
  • 4KB Block Erase is good for small data storage, code shadowing and direct XiP solutions

For more information on this topic check out our recent Serial NOR flash webinar.

Sundar Ranganathan is a Sr. Product Marketing Manager at Micron Technology, Inc. He helps with the memory business in Japan and America regions.

Amit Gattani

Sundar Ranganathan